[bgoldbug]

• Changed dev command into update_rtl command. Now, after tracking design updates via update_rtl, the user will be notified that RTL has been updated, and the flow is no longer run after changes are tracked.
  • DEV_FLAG logic was removed from verilog.mk files (and any file generation logic for that matter), and Verilog generation for all designs was incorporated into the setup.sh script. This is NECESSARY, as update_rtl no longer runs the flow, thus verilog.mk won't be triggered by update_rtl.
    • verilog.mk now only holds technology-independent Verilog RTL logic.
    • This should also help any issues using update_rtl.sh for Bazel.
• Added vortex, coralnpu, and NVDLA (small configuration) partitions to the suite (ASAP7).
• Added FakeRAM submodule and corresponding setup logic
• Updated README and added HighTide logo
• Consolidated Markdown documents into a docs folder
• Added a GitHub action that checks if required design files were added

[mguthaus]

Closing in favor of smaller follow-up PRs.

This branch predates the Bazel flow migration on main (#45+), and the new designs added here (vortex, coralnpu, NVDLA) need Bazel BUILD files to work in the current flow. The Make-flow-only infra changes (Makefile, settings.mk, setup.sh, runorfs.sh renames, dev → update_rtl, docs reorg) have also been largely superseded by the Bazel migration.

Rather than force this large branch through a messy merge, we'll re-land the new designs individually using the current new-design workflow:

• Vortex (asap7) — separate PR
• CoralNPU (asap7) — separate PR
• NVDLA (asap7) — separate PR(s), one per partition as appropriate

The suite-update branch is preserved as reference for the original RTL captures and SRAM LEF/LIB files. Thanks @bgoldbug for the original work — we'll carry it forward, just split up and adapted to Bazel.