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Add Vortex GPGPU design on asap7 - #60
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Points designs/src/vortex/dev/repo at upstream vortexgpgpu/vortex.git (commit 31e4765d — matches the snapshot captured in the closed PR #37 suite-update branch). Dev-mode regeneration requires the user to init this submodule first: git submodule update --init designs/src/vortex/dev/repo
Pinned snapshot of upstream vortex hw/rtl/ (commit 31e4765d, minus the
afu/ and tcu/ subsystems which require vendor AFU headers / optional
tensor-core extension). VX_dp_ram.sv and VX_sp_ram.sv have been swapped
for FakeRAM-aware variants that instantiate the fakeram_* macros above
a bit-count threshold; their original (upstream) bodies live under
dev/VX_{dp,sp}_ram_REPLACE.sv as the overlay applied by dev/setup.sh.
- srcs.bzl: ordered SV file list + include-dir strings for release and
dev modes. Order follows vortex hw/rtl Makefile (packages -> interfaces
-> libs -> cache -> fpu -> mem -> core -> top). Excludes five
libs/VX_*_adapter.sv files that are only used by Vortex_axi / the
OPAE AFU (both excluded tops).
- BUILD.bazel: rtl_release + rtl_dev filegroups plus rtl_data_* for
include-dir resolution; select() on //:update_rtl switches modes.
- verilog.mk: Make-flow equivalent using SYNTH_HDL_FRONTEND=slang with
the same include dirs, defines, and file list.
- dev/setup.sh: copies the submodule's hw/rtl/ into dev/gen/rtl/ and
overlays the *_REPLACE.sv stubs. Run manually before bazel build
--define update_rtl=true. Replaces the closed PR's buggy
cp-into-pwd setup.sh.
- dev/install/install_sv2v.sh: optional prebuilt sv2v downloader — not
required for the primary yosys-slang path, kept for alternate flows.
Wires Vortex up as a HighTide2 asap7 benchmark with both flows sharing
constraint.sdc / io.tcl and the sram/ FakeRAM tree.
Parameters carried forward from the closed suite-update PR:
- Top: Vortex (not Vortex_axi)
- CORE_UTILIZATION = 50, MACRO_PLACE_HALO = 5 5
- PLACE_DENSITY_LB_ADDON = 0.46, TNS_END_PERCENT = 100
- Clock: 1100 ps on 'clk' (set in constraint.sdc), set_max_fanout 32
- Frontend: yosys-slang (SYNTH_HDL_FRONTEND=slang), SYNTH_HIERARCHICAL=0
- Defines: SYNTHESIS, SV_DPI, MEM_BLOCK_SIZE=16, MAX_FANOUT=32,
LATENCY_IMUL=5
io.tcl uses OpenROAD's place_pin (singular) to pin the memory request
bus to the right edge, response bus to the left, clk/reset to top, and
dcr_*/busy to bottom; this requires the FOOTPRINT_TCL escape hatch to
keep io_placement.tcl from re-running place_pins.
sram/{lef,lib}/ carries 12 FakeRAM pairs generated for asap7; the eight
actually referenced by ADDITIONAL_LEFS/LIBS cover the vortex L1I/L1D,
dcache data banks, register file, and LSU buffers for the default
config. The remaining four (21x64, 560x4, 654x4, 87x16) are retained
from the closed PR for experimentation with alternate configurations
and are benign when unreferenced.
# Conflicts: # .gitmodules
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Summary
Adds the Vortex open-source GPGPU as an asap7 benchmark design in HighTide2, with both Bazel and Make flow support. Split out from closed PR #37, adapted to the current Bazel-primary flow (closed PR predated the Bazel migration).
vortexgpgpu/vortex @ 31e4765d(pinned submodule atdesigns/src/vortex/dev/repo)Vortex, clock 1100 ps, flat synthesis (SYNTH_HIERARCHICAL=0)afu/andtcu/pruned), yosys-slang frontenddesigns/src/vortex/BUILD.bazel(rtl_release / rtl_dev_gen / rtl alias on //:update_rtl) +designs/asap7/vortex/BUILD.bazelviahightide_design()designs/asap7/vortex/config.mk+verilog.mkTest plan
mrg-hightide-asap7-vortex(NRP Nautilus): full RTL→GDS flow completed (2h 12m, 34/34 Bazel actions)--define update_rtl=true) not yet exercised end-to-end — release RTL is the validated pathNotes
designs/src/vortex/BUILD.bazelcontained NyuziProcessor content (template paste error); this PR writes fresh, validated Bazel files.dev/setup.shhad buggycppaths; rewritten cleanly to copyhw/rtl/intodev/gen/rtl/withVX_dp_ram/VX_sp_ramFakeRAM substitutions overlaid.