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NVDLA (NVIDIA Deep Learning Accelerator, nv_small config) sources are pinned at github.com/nvdla/hw#nv_small commit 771f20cc. dev/setup.sh installs OpenJDK 11, OpenSSL 1.0.2u, Perl 5.10.1, Python 2.7.18, and SystemC 2.3.0 locally under dev/packages/, then runs `perl tools/bin/tmake -build vmod` and substitutes a pre-baked NV_NVDLA_cfgrom.v (the upstream cfgrom file is auto-generated and contains an enum literal yosys parses incorrectly). Pre-generated release RTL is committed in a follow-up commit so the dev path is opt-in.
Commits the vmod/ tree generated by `tmake -build vmod` against the
nv_small project. Synthesis consumes vmod/{rams/synth,vlibs,nvdla}
plus macros.v (per verilog.mk); vmod/rams/{model,fpga} are
simulation-only and would not be generated by the dev path either.
macros.v provides FakeRAM wrappers (RAMDP_*/RAMPDP_*) bridging the
NVDLA RAM port names to the asap7 fakeram pins.
verilog.mk: fix VERILOG_INCLUDE_DIRS — original used an undefined
$(VMOD), should glob under vmod/ to pick up include/ and vlibs/ .vh
files (NV_HWACC_NVDLA_tick_defines.vh, simulate_x_tick.vh,
assertion_*.vh).
BUILD.bazel exposes :rtl as a release-only filegroup. Dev-mode
generation is intentionally not wired as a Bazel genrule because
setup.sh downloads multi-hundred-MB toolchains and runs for hours;
run setup.sh manually and re-stage vmod/ to refresh.
.vcp source files (the pre-tmake `vlib` inputs, identical content to
the .v outputs) were trimmed — only .v files are read by the flow.
~57 fakeram_<W>x<D>_1r1w pairs covering the union of macros referenced
across all 5 partitions. Per-partition subsets are exposed as
:sram_lefs_{a,c,o,p} / :sram_libs_{a,c,o,p} filegroups (mirroring the
ADDITIONAL_LEFS/LIBS lists in each partition's config.mk). partition_m
references no FakeRAM so it pulls neither.
A :sram_lefs_all / :sram_libs_all pair is also exposed for any
consumer that wants the full set.
Five top-level partitions of NVDLA nv_small. All share the same vmod RTL via DESIGN_NICKNAME=NVDLA + DESIGN_RESULTS_NAME=NVDLA_partition_X in config.mk; on the Bazel side each partition is a separate hightide_design() that pulls //designs/src/NVDLA:rtl with its own SDC and FakeRAM subset. Per-partition tuning (from closed PR #37): a: util=55, density+0.20, halo=5, FakeRAM={256x16,272x16} c: util=50, density+0.25, halo=2, FakeRAM={64x256,64x16,6x128, 66x8,11x128} m: util=55, density+0.20, halo=5, no FakeRAM o: util=45, density+0.15, halo=7, FakeRAM={18x128,8x256,4x256, 7x256,66x64,15x80,22x60, 32x128,9x80}, two clocks (core 2000ps + falcon 2500ps) p: util=45, density+0.25, halo=5, FakeRAM={16x160,65x160,14x80,66x80} All partitions: SYNTH_HIERARCHICAL=1, TNS_END_PERCENT=100, single 1500ps nvdla_core_clk except partition_o.
The release PR copied the reset/clock ideal-network list twice; remove the duplicate block. Cosmetic cleanup, no functional change.
Yosys on Nautilus failed with "Can't open include file 'simulate_x_tick.vh'" because VERILOG_INCLUDE_DIRS pointed at dirs that were never staged into the Bazel action sandbox. The :rtl filegroup ships .v files only, so headers lived outside the inputs. - designs/src/NVDLA:include now globs both vmod/include/*.vh and vmod/vlibs/*.vh (vlibs is on VERILOG_INCLUDE_DIRS too). - Each partition BUILD.bazel passes //designs/src/NVDLA:include via stage_data['synth'] (same pattern bp_processor uses for its header tree).
partition_c synth/floorplan/place/CTS all completed on Nautilus, but post-CTS detailed-placement legalization failed on 1/140726 cells (a clkbuf adjacent to cbuf_ram_bank31). Align the tuning knobs with partition_a/p, which both legalized end-to-end: CORE_UTILIZATION 50 -> 45 PLACE_DENSITY_LB_ADDON 0.25 -> 0.30 MACRO_PLACE_HALO 2 2 -> 5 5
halo=2 failed DPL legalization (1 clkbuf near cbuf_ram_bank31 had no slot). halo=5 then failed MPL-0003 "no valid tilings" with 84 macros — too much halo area. Try an intermediate halo with a small die bump: CORE_UTILIZATION 50 -> 48 (keep die almost the same) PLACE_DENSITY_LB_ADDON 0.30 -> 0.25 (back to original) MACRO_PLACE_HALO 5 5 -> 3 3 If this also fails, STOP and document in REPORT per PROMPT3.
Attempt 3 (util=48 halo=3) reached global routing but hit GRT-0116 "finished with congestion". Enlarge the die: CORE_UTILIZATION 48 -> 40 PLACE_DENSITY_LB_ADDON 0.25 -> 0.30 MACRO_PLACE_HALO 3 3 (unchanged)
# Conflicts: # .gitmodules
This was referenced Apr 19, 2026
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Summary
Adds NVIDIA's NVDLA (Deep Learning Accelerator,
nv_smallconfig) as an asap7 benchmark to HighTide. NVDLA is split into 5 partitions (a, c, m, o, p), each a separate top-level design sharing one source tree and a pool of 57 FakeRAM LEF/LIB pairs. Split out from closed PR #37, adapted to the current Bazel-primary flow.nvdla/hw#nv_small @ 771f20cc(pinned submodule)SYNTH_HIERARCHICAL=1on all partitionspartition_oruns two clocks (nvdla_core_clk2000 ps,nvdla_falcon_clk2500 ps); others use a single 1500 psnvdla_core_clkPer-partition verification (NRP Nautilus K8s, full RTL→GDS)
NV_NVDLA_partition_aNV_NVDLA_partition_cNV_NVDLA_partition_mNV_NVDLA_partition_oNV_NVDLA_partition_ppartition_c tuning journey (the hard one — 84 macros on an asap7 die)
DPL-0036: clkbuf couldn't legalize nearcbuf_ram_bank31MPL-0003: no valid tilings (halo×84 ate tiling budget)GRT-0116: placed but routed-congestedTraded peak util for flow completion. PPA sweep is a follow-up.
Fixes / deviations from closed PR #37
hightide_design()calls, per-partition SRAM filegroups, shareddesigns/src/NVDLA/BUILD.bazelexposing:rtl,:rtl_release,:include.stage_data = {\"synth\": [\"//designs/src/NVDLA:include\"]}on each partition so yosys can resolve.vhheaders in the Bazel sandbox (otherwise fails withCan't open include file 'simulate_x_tick.vh').verilog.mk— wasfind \$(VMOD) -name \"*.vh\"where\$(VMOD)is undefined. Changed tofind \$(BENCH_DESIGN_HOME)/src/NVDLA/vmod -name \"*.vh\"..vcpfiles — upstream tmake preprocessor inputs, never consumed by the flow. Source tree drops from 1072 → 527 vmod files.set_ideal_networkblock inpartition_c/constraint.sdc(was repeated 2×).Test plan
bazel build :partition_X_finalon Nautilus K8spartition_c(currently 42% util) — follow-uppartition_oSDC usesset_false_pathbetween clocks instead ofset_clock_groups -asynchronous— works end-to-end, idiomatic cleanup is a nitFollow-ups
partition_cnangate45/sky130hd(scoped to asap7 here)