[liorgold2]

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Stack:

• Test that every (main) trace column is used in the constraints. #670 ⬅

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⚠️ Part of a stack created by spr. Do not merge manually using the UI - doing so may have unexpected results.

[cursor]

PR Summary

Low Risk
Changes are limited to debug metadata and test-time circuit analysis assertions; verifier proof logic is unchanged aside from storing OODS trace vars for analysis.

Overview
Adds a circuit analysis check that every main-trace column sampled at the OODS point is wired into the composition polynomial (via the composition_eval add/mul dependency cone).

To support that, DebugInfo gains a lists map for named Vec<Var>, and verify records proof.trace_at_oods under "trace_at_oods" before the existing logup-summand validation runs.

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[anatgstarkware]

@anatgstarkware reviewed 3 files and all commit messages, and made 1 comment.
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[liorgold2]

@liorgold2 reviewed 1 file and all commit messages.
Reviewable status: complete! all files reviewed, all discussions resolved (waiting on liorgold2).