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Revert "neon riscv64: Enable RVV segment load/store only when we have… - #1353
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… `__riscv_zvlsseg` flag. (simd-everywhere#1285)" This reverts commit 3e5facc.
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Previously, we applied this workaround to support CPUs that lack segment load/store instructions. To align with the current standard and because we no longer support simde on those CPUs, I reverted the PR.
This reverts commit 3e5facc.