feat(riscv64): support dynamic platform on QEMU and SG2002

apps/starry/orangepi-5-plus-uvc-rknn/build-aarch64-unknown-none-softfloat.toml

@@ -2,10 +2,8 @@
 target = "aarch64-unknown-none-softfloat"
 env = {}
 features = [
-  "ax-hal/plat-dyn",
-  "starry-kernel/plat-dyn",
   "ax-driver/irq",
-  "ax-driver/pci-list-devices",
+  "ax-driver/list-pci-devices",
   "ax-driver/rk3588-pcie",
   "ax-driver/realtek-rtl8125",
   "ax-driver/rockchip-soc",

apps/starry/orangepi-5-plus-uvc/build-aarch64-unknown-none-softfloat.toml

@@ -2,8 +2,6 @@
 target = "aarch64-unknown-none-softfloat"
 env = {}
 features = [
-  "ax-hal/plat-dyn",
-  "starry-kernel/plat-dyn",
   "ax-driver/rockchip-soc",
   "ax-driver/rockchip-dwc-xhci",
   "ax-driver/rockchip-sdhci",

components/axcpu/src/exception_table.rs

@@ -3,13 +3,13 @@ use crate::TrapFrame;
 #[repr(C)]
 #[derive(Debug, PartialEq, Eq)]
 struct ExceptionTableEntry {
-    #[cfg(target_arch = "aarch64")]
+    #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))]
     from: i32,
-    #[cfg(target_arch = "aarch64")]
+    #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))]
     to: i32,
-    #[cfg(not(target_arch = "aarch64"))]
+    #[cfg(not(any(target_arch = "aarch64", target_arch = "riscv64")))]
     from: usize,
-    #[cfg(not(target_arch = "aarch64"))]
+    #[cfg(not(any(target_arch = "aarch64", target_arch = "riscv64")))]
     to: usize,
 }
 
@@ -22,7 +22,13 @@ impl ExceptionTableEntry {
             (base + self.from as isize) as usize
         }
 
-        #[cfg(not(target_arch = "aarch64"))]
+        #[cfg(target_arch = "riscv64")]
+        {
+            let base = unsafe { _ex_table_start.as_ptr() } as isize;
+            (base + self.from as isize) as usize
+        }
+
+        #[cfg(not(any(target_arch = "aarch64", target_arch = "riscv64")))]
         {
             self.from
         }
@@ -36,7 +42,13 @@ impl ExceptionTableEntry {
             (base + self.to as isize) as usize
         }
 
-        #[cfg(not(target_arch = "aarch64"))]
+        #[cfg(target_arch = "riscv64")]
+        {
+            let base = unsafe { _ex_table_start.as_ptr() } as isize;
+            (base + self.to as isize) as usize
+        }
+
+        #[cfg(not(any(target_arch = "aarch64", target_arch = "riscv64")))]
         {
             self.to
         }

components/axcpu/src/riscv/macros.rs

@@ -15,8 +15,8 @@ macro_rules! __asm_macros {
         .macro _asm_extable, from, to
             .pushsection __ex_table, "a"
             .balign 4
-            .word   \from
-            .word   \to
+            .word   \from - _ex_table_start
+            .word   \to - _ex_table_start
             .popsection
         .endm
 
@@ -40,9 +40,9 @@ macro_rules! __asm_macros {
 
         .macro _asm_extable, from, to
             .pushsection __ex_table, "a"
-            .balign 8
-            .quad   \from
-            .quad   \to
+            .balign 4
+            .word   \from - _ex_table_start
+            .word   \to - _ex_table_start
             .popsection
         .endm
 

components/someboot/Cargo.toml

@@ -14,6 +14,7 @@ efi = []
 hv = []
 mmu = []
 percpu-prealloc = []
+thead-mae = []
 uspace = ["mmu"]
 
 [dependencies]

components/someboot/build.rs

@@ -40,7 +40,6 @@ fn main() {
     } else if build.uspace {
         println!("cargo:rustc-cfg=uspace");
     }
-
     if build.page_size == 4096 {
         println!("cargo:rustc-cfg=page_size_4k");
     } else if build.page_size == 16384 {
@@ -158,7 +157,7 @@ impl Build {
     fn prepare_riscv64(&mut self) {
         let ld_src = "src/arch/riscv64/link.ld";
 
-        if self.uspace {
+        if self.uspace || self.hv {
             self.kernel_vaddr = 0xffff_ffff_8000_0000;
         } else {
             self.kernel_vaddr = 0x8020_0000;

components/someboot/src/acpi/mod.rs

@@ -35,6 +35,11 @@ fn rsdp() -> Option<NonNull<u8>> {
     NonNull::new(ptr)
 }
 
+pub fn rsdp_addr_phys() -> Option<usize> {
+    let rsdp = unsafe { RSDP };
+    (rsdp != 0).then_some(rsdp)
+}
+
 pub fn tables() -> Result<AcpiTables<AcpiHandle>, acpi::AcpiError> {
     unsafe {
         let rsdp = if RSDP == 0 {

components/someboot/src/arch/aarch64/paging/mod.rs

@@ -26,7 +26,7 @@ pub fn enable_mmu() -> ! {
     let mmu_entry_phys = super::entry::mmu_entry as *const () as usize;
     println!("MMU Entry point at physical address: {:#x}", mmu_entry_phys);
 
-    let meta = crate::smp::cpu_meta(crate::smp::cpu_idx()).unwrap();
+    let meta = crate::smp::cpu_meta(crate::smp::early_current_cpu_idx()).unwrap();
     let v_sp = meta.stack_top_virt;
     let v_entry = __kimage_va(mmu_entry_phys) as usize;
 

components/someboot/src/arch/riscv64/addrspace.rs

@@ -1,11 +1,11 @@
 include!(concat!(env!("OUT_DIR"), "/defines.rs"));
 
-#[cfg(uspace)]
+#[cfg(any(uspace, hv))]
 pub const PAGE_OFFSET: usize = 0xffff_ffc0_0000_0000;
-#[cfg(not(uspace))]
+#[cfg(not(any(uspace, hv)))]
 pub const PAGE_OFFSET: usize = 0;
 
-#[cfg(uspace)]
+#[cfg(any(uspace, hv))]
 pub const PERCPU_BASE: usize = 0xffff_ffe0_0000_0000;
-#[cfg(not(uspace))]
+#[cfg(not(any(uspace, hv)))]
 pub const PERCPU_BASE: usize = PAGE_OFFSET;

components/someboot/src/arch/riscv64/entry.rs

@@ -50,7 +50,8 @@ pub unsafe extern "C" fn kernel_entry(_hart_id: usize, _fdt_addr: usize) -> ! {
         "mv t0, a1",
         "lla sp, __cpu0_stack_top",
         "mv a0, t0",
-        "j {primary_head_entry}",
+        "lla t1, {primary_head_entry}",
+        "jr t1",
         primary_head_entry = sym primary_head_entry,
     )
 }
@@ -98,7 +99,8 @@ pub(crate) unsafe extern "C" fn _secondary_entry(_hartid: usize, _cpu_meta_paddr
         "mv t0, a1",
         "ld sp, {stack_top_offset}(t0)",
         "mv a0, t0",
-        "j {secondary_start}",
+        "lla t1, {secondary_start}",
+        "jr t1",
         secondary_start = sym secondary_start,
         stack_top_offset = const offset_of!(PerCpuMeta, stack_top),
     )

components/someboot/src/arch/riscv64/link.ld

@@ -1,5 +1,5 @@
 PROVIDE(PAGE_SIZE = 0x1000);
-PROVIDE(STACK_SIZE = 0x4000);
+PROVIDE(STACK_SIZE = 0x40000);
 VM_LOAD_ADDRESS = ${kernel_load_vaddr};
 
 OUTPUT_ARCH(riscv)
@@ -54,6 +54,21 @@ SECTIONS
     _edata = .;
     __kernel_load_end = .;
     __bss_start = .;
+
+    .tdata : {
+        _stdata = .;
+        *(.tdata .tdata.*)
+        _etdata = .;
+    }
+
+    .tbss : {
+        _stbss = .;
+        *(.tbss .tbss.*)
+        *(.init.bss)
+        *(.tcommon)
+        _etbss = .;
+    }
+
     .sbss : {
         *(.dynsbss)
         *(.sbss .sbss.*)

components/someboot/src/arch/riscv64/mod.rs

@@ -13,15 +13,15 @@ mod trap;
 use core::sync::atomic::{AtomicUsize, Ordering};
 
 pub(crate) use entry::_secondary_entry;
-use page_table_generic::{PageTableEntry, PhysAddr, PteConfig, TableMeta, VirtAddr};
+use page_table_generic::{MemAttributes, PageTableEntry, PhysAddr, PteConfig, TableMeta, VirtAddr};
 pub use relocate::apply as relocate;
 
 use crate::{
     ArchTrait, DCacheOp,
     mem::{PageTableInfo, mmu},
     power::CpuOnError,
 };
-#[cfg(uspace)]
+#[cfg(any(uspace, hv))]
 use crate::{mem::__kimage_va_to_pa, smp::percpu_va_range};
 
 const KERNEL_LOAD_ADDRESS: usize = 0x8020_0000;
@@ -37,10 +37,59 @@ const PTE_U: usize = 1 << 4;
 const PTE_G: usize = 1 << 5;
 const PTE_A: usize = 1 << 6;
 const PTE_D: usize = 1 << 7;
+const PTE_PPN_MASK: usize = (1 << 44) - 1;
+
+#[cfg(feature = "thead-mae")]
+const PTE_THEAD_SEC: usize = 1 << 59;
+#[cfg(feature = "thead-mae")]
+const PTE_THEAD_SH: usize = 1 << 60;
+#[cfg(feature = "thead-mae")]
+const PTE_THEAD_B: usize = 1 << 61;
+#[cfg(feature = "thead-mae")]
+const PTE_THEAD_C: usize = 1 << 62;
+#[cfg(feature = "thead-mae")]
+const PTE_THEAD_SO: usize = 1 << 63;
+#[cfg(feature = "thead-mae")]
+const PTE_THEAD_PMA: usize = PTE_THEAD_C | PTE_THEAD_B | PTE_THEAD_SH;
+#[cfg(feature = "thead-mae")]
+const PTE_THEAD_NOCACHE: usize = PTE_THEAD_B | PTE_THEAD_SH;
+#[cfg(feature = "thead-mae")]
+const PTE_THEAD_IO: usize = PTE_THEAD_SO | PTE_THEAD_SH;
+#[cfg(feature = "thead-mae")]
+const PTE_THEAD_MT_MASK: usize =
+    PTE_THEAD_SEC | PTE_THEAD_SH | PTE_THEAD_B | PTE_THEAD_C | PTE_THEAD_SO;
 
 static KERNEL_PAGE_TABLE_ADDR: AtomicUsize = AtomicUsize::new(0);
 static TIMEBASE_FREQ: AtomicUsize = AtomicUsize::new(0);
 
+#[cfg(feature = "thead-mae")]
+fn thead_mae_pte_bits(mem_attr: MemAttributes) -> usize {
+    match mem_attr {
+        MemAttributes::Device => PTE_THEAD_IO,
+        MemAttributes::Uncached => PTE_THEAD_NOCACHE,
+        MemAttributes::Normal | MemAttributes::PerCpu => PTE_THEAD_PMA,
+    }
+}
+
+#[cfg(not(feature = "thead-mae"))]
+fn thead_mae_pte_bits(_mem_attr: MemAttributes) -> usize {
+    0
+}
+
+#[cfg(feature = "thead-mae")]
+fn thead_mae_mem_attr(bits: usize) -> MemAttributes {
+    match bits & PTE_THEAD_MT_MASK {
+        PTE_THEAD_IO => MemAttributes::Device,
+        PTE_THEAD_NOCACHE => MemAttributes::Uncached,
+        _ => MemAttributes::Normal,
+    }
+}
+
+#[cfg(not(feature = "thead-mae"))]
+fn thead_mae_mem_attr(_bits: usize) -> MemAttributes {
+    MemAttributes::Normal
+}
+
 #[derive(Clone, Copy, Debug, Default)]
 #[repr(transparent)]
 pub struct Entry(usize);
@@ -75,9 +124,10 @@ impl PageTableEntry for Entry {
             if config.writable || config.dirty {
                 bits |= PTE_D;
             }
+            bits |= thead_mae_pte_bits(config.mem_attr);
         }
 
-        bits |= (config.paddr.raw() >> 12) << SV39_PPN_SHIFT;
+        bits |= ((config.paddr.raw() >> 12) & PTE_PPN_MASK) << SV39_PPN_SHIFT;
         Self(bits)
     }
 
@@ -91,7 +141,7 @@ impl PageTableEntry for Entry {
         let global = (bits & PTE_G) != 0;
         let dirty = (bits & PTE_D) != 0;
         let huge = is_dir && (read || writable || executable);
-        let paddr = PhysAddr::new((bits >> SV39_PPN_SHIFT) << 12);
+        let paddr = PhysAddr::new(((bits >> SV39_PPN_SHIFT) & PTE_PPN_MASK) << 12);
 
         PteConfig {
             paddr,
@@ -104,7 +154,7 @@ impl PageTableEntry for Entry {
             global,
             is_dir,
             huge,
-            mem_attr: Default::default(),
+            mem_attr: thead_mae_mem_attr(bits),
         }
     }
 
@@ -176,7 +226,7 @@ impl ArchTrait for Arch {
 
     fn virt_to_phys(vaddr: *const u8) -> usize {
         let vaddr = vaddr as usize;
-        #[cfg(uspace)]
+        #[cfg(any(uspace, hv))]
         {
             if mmu::is_mmu_enabled() {
                 if percpu_va_range().contains(&vaddr) {
@@ -237,10 +287,6 @@ impl ArchTrait for Arch {
     }
 
     fn cpu_on(hartid: usize, entry: usize, arg: usize) -> Result<(), CpuOnError> {
-        if hartid == Self::cpu_current_hartid() {
-            return Err(CpuOnError::AlreadyOn);
-        }
-
         match sbi::hart_start(hartid, entry, arg) {
             Ok(()) => Ok(()),
             Err(sbi::HartStartError::AlreadyAvailable | sbi::HartStartError::AlreadyStarted) => {

components/someboot/src/arch/riscv64/paging.rs

@@ -15,7 +15,7 @@ pub fn enable_mmu() -> ! {
     }
 
     let mmu_entry_phys = super::entry::mmu_entry as *const () as usize;
-    let meta = crate::smp::cpu_meta(crate::smp::cpu_idx()).unwrap();
+    let meta = crate::smp::cpu_meta(crate::smp::early_current_cpu_idx()).unwrap();
     let v_sp = meta.stack_top_virt;
     let v_entry = __kimage_va(mmu_entry_phys) as usize;
 

components/someboot/src/arch/riscv64/trap.rs

@@ -3,7 +3,6 @@ use core::{arch::global_asm, mem::offset_of};
 use crate::irq;
 
 const SCAUSE_INTERRUPT_BIT: usize = 1usize << (usize::BITS as usize - 1);
-const SCAUSE_SUPERVISOR_TIMER: usize = 5;
 
 #[repr(C)]
 struct TrapFrame {
@@ -66,11 +65,8 @@ pub fn trap_addr() -> usize {
 extern "C" fn __riscv64_handle_trap(tf: &mut TrapFrame) {
     let scause = tf.scause;
     if (scause & SCAUSE_INTERRUPT_BIT) != 0 {
-        let cause = scause & !SCAUSE_INTERRUPT_BIT;
-        if cause == SCAUSE_SUPERVISOR_TIMER {
-            irq::handle_irq(irq::systimer_irq());
-            return;
-        }
+        irq::handle_irq(irq::IrqId::new(scause));
+        return;
     }
 
     panic!(

components/someboot/src/arch/x86_64/paging.rs

@@ -124,7 +124,7 @@ pub fn enable_mmu() -> ! {
         panic!("failed to setup x86_64 page table: {err:?}");
     }
 
-    let meta = crate::smp::cpu_meta(crate::smp::cpu_idx()).unwrap();
+    let meta = crate::smp::cpu_meta(crate::smp::early_current_cpu_idx()).unwrap();
     let v_sp = meta.stack_top_virt;
     let v_entry = __kimage_va(super::entry::mmu_entry as *const () as usize) as usize;
 

components/someboot/src/arch/x86_64/power.rs

@@ -132,8 +132,15 @@ pub(crate) fn notify_ap_started(apic_id: usize) {
     AP_BOOTED_ID.store(apic_id, Ordering::Release);
 }
 
+fn current_apic_id() -> usize {
+    x86::cpuid::CpuId::new()
+        .get_feature_info()
+        .map(|info| info.initial_local_apic_id() as usize)
+        .unwrap_or(0)
+}
+
 pub(crate) fn cpu_on(apic_id: usize, entry: usize, arg: usize) -> Result<(), CpuOnError> {
-    if apic_id == crate::smp::cpu_hart_id() {
+    if apic_id == current_apic_id() {
         return Err(CpuOnError::AlreadyOn);
     }
     let apic_id = u8::try_from(apic_id).map_err(|_| CpuOnError::InvalidParameters)?;

components/someboot/src/fdt/earlycon.rs

@@ -59,7 +59,7 @@ fn set_by_stdout() -> Option<()> {
                 installed = true;
                 break;
             }
-            "snps,dw-apb-uart" => {
+            "snps,dw-apb-uart" | "ns16550a" | "ns16550" => {
                 let mut serial = ns16550::Ns16550::new_mmio(addr, clock, reg_width);
                 serial.open();
                 let tx = serial.take_tx()?;