DMA: support for various STM32 DMA controllers

configs/stm32f429i_disc1_autotest_defconfig

@@ -6,3 +6,4 @@ CONFIG_STANDALONE_MODE=y
 CONFIG_BUILD_TARGET_AUTOTEST=y
 CONFIG_TEST_IRQ=y
 CONFIG_TEST_CAPA=y
+CONFIG_TEST_DMA=y

dts/examples/stm32f429i_disc1_autotest.dts

@@ -18,7 +18,7 @@
 	};
 
 	reserved-memory {
-		autotest_code: autotest_code@800e000 {
+		autotest_code: autotest_code@8010000 {
 			reg = <0x8010000 0x10000>;
 			compatible = "sentry,memory-pool";
 		};
@@ -63,6 +63,43 @@
 			sentry,label = <0xf03>;
 			sentry,owner = <0xbabe>;
 		};
+		dma-streams {
+			// device-to-memory DMA stream
+			stream1 {
+				compatible = "dma-stream";
+				channel = <&dma1_1>;
+				streamid = <3>; // channel stream (af) identifier
+				prio = <STM32_DMA_PRIORITY_MEDIUM>;
+				source = <&usart1>;
+				dest = <&shm_autotest_1>;
+				length = <42>;
+				circular = <1 0>; // circular source, linear dest
+				sentry,label = <0x1>; // task-level unique DMA identifier
+			};
+			// memory-to-memory DMA stream
+			stream2 {
+				compatible = "dma-stream";
+				channel = <&dma1_1>;
+				streamid = <1>; // channel stream (af) identifier
+				prio = <STM32_DMA_PRIORITY_MEDIUM>;
+				source = <&shm_autotest_1>;
+				dest = <&shm_autotest_2>;
+				length = <42>;
+				circular = <1 0>; // circular source, linear dest
+				sentry,label = <0x2>; // task-level unique DMA identifier
+			};
+		};
+	};
+};
+
+&dma1 {
+	status = "okay";
+	// STM32F4 DMA has 8 channels
+	dma-channels = <8>;
+	// About channels that are used
+	dma1_1: dma-channel@1 {
+		status = "okay";
+		sentry,owner = <0xbabe>;
 	};
 };
 

dts/sentry.dtsi

@@ -17,7 +17,7 @@
 		#size-cells = <1>;
 
 		kernel_code: kernel_code@8000000 {
-			reg = <0x8000000 0xb800>;
+			reg = <0x8000000 0xc000>;
 			compatible = "sentry,memory-pool";
 		};
 

kernel/src/arch/asm-cortex-m/Kconfig

@@ -97,6 +97,8 @@ config SOC_SUBFAMILY_STM32F4
 	select HAS_DCACHE
 	select HAS_ICACHE
 	select HAS_MPU_PMSA_V7
+	select HAS_GPDMA
+	select HAS_GPDMA_ST_DMAV1
 	help
 	  STM32F4 family is based on Cortex-M4 with FPU and PMSAv7 MPU.
 
@@ -111,6 +113,8 @@ config SOC_SUBFAMILY_STM32L4
 	select HAS_DCACHE
 	select HAS_ICACHE
 	select HAS_RNG
+	select HAS_GPDMA
+	select HAS_GPDMA_ST_DMAV2
 	help
 	  STM32L4 family is based on Cortex-M4 with FPU and PMSAv7 MPU with low power features
 
@@ -136,6 +140,8 @@ config SOC_SUBFAMILY_STM32WB
 	select HAS_MPU
 	select HAS_RNG
 	select HAS_MPU_PMSA_V7
+	select HAS_GPDMA
+	select HAS_GPDMA_ST_DMAV2
 	# Cache support ?
 	help
 	  STM32WB family is based on Cortex-M4 (main core and a Cortex-M0+ for wireless core)
@@ -318,4 +324,4 @@ config RUSTC_TARGET
 	default "thumbv8m.main-none-eabi" if ARCH_ARM_ARMV8MML && !FPU_HARDFP_ABI
 	default "thumbv8m.main-none-eabihf" if ARCH_ARM_ARMV8MML && FPU_HARDFP_ABI
 
-endmenu
+endmenu

kernel/src/arch/asm-generic/Kconfig

@@ -42,9 +42,18 @@ config HAS_RNG
 config HAS_GPDMA
 	bool
 
+config HAS_GPDMA_ST_DMAV1
+	bool
+	depends on HAS_GPDMA
+
+config HAS_GPDMA_ST_DMAV2
+	bool
+	depends on HAS_GPDMA
+
+
 config SYSTICK_HZ
 	int "systick initial period configuration"
 	range 0 10000
 	default 1000
 
-endmenu
+endmenu

kernel/src/drivers/dma/meson.build

@@ -1,6 +1,11 @@
 # SPDX-FileCopyrightText: 2023 Ledger SAS
+# SPDX-FileCopyrightText: 2026 H2Lab Development Team
 # SPDX-License-Identifier: Apache-2.0
 
+# for U5A5 GPDMA implementation, the register definitions are generated from the SVD file using jinja templates.
+# This allows us to have a single source of truth for the register definitions and avoid manual errors.
+if kconfig_data.get('CONFIG_SOC_SUBFAMILY_STM32U5', 0) == 1
+
 gpdma_h = custom_target('gen_gpdma',
     input: peripheral_defs_in,
     output: '@0@_defs.h'.format('gpdma'),
@@ -11,18 +16,43 @@ gpdma_h = custom_target('gen_gpdma',
        '@INPUT@'
     ],
 )
-
 bsp_private_gen_header_set.add(gpdma_h)
 
+endif
+
+
+
 stm32_gpdma_dts_template_c = files(['stm32-gpdma-dt.c.in'])
 stm32_gpdma_dts_template_h = files(['stm32-gpdma-dt.h.in'])
 
 stm32_gpdma_dtsgen_c = dtsgen.process(stm32_gpdma_dts_template_c)
 stm32_gpdma_dtsgen_h = dtsgen.process(stm32_gpdma_dts_template_h)
 
+# st-dma-v1 DTS-based controller definitions generation
+stm32_dma_v1_dts_template_c = files(['stm32-st-dmav1-dt.c.in'])
+stm32_dma_v1_dts_template_h = files(['stm32-st-dmav1-dt.h.in'])
 
-bsp_private_gen_source_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32U5', if_true: [ stm32_gpdma_dtsgen_c, stm32_gpdma_dtsgen_h ])
+stm32_dma_v1_dtsgen_c = dtsgen.process(stm32_dma_v1_dts_template_c)
+stm32_dma_v1_dtsgen_h = dtsgen.process(stm32_dma_v1_dts_template_h)
 
+# st-dma-v2 DTS-based controller definitions generation
+stm32_dma_v2_dts_template_c = files(['stm32-st-dmav2-dt.c.in'])
+stm32_dma_v2_dts_template_h = files(['stm32-st-dmav2-dt.h.in'])
+
+stm32_dma_v2_dtsgen_c = dtsgen.process(stm32_dma_v2_dts_template_c)
+stm32_dma_v2_dtsgen_h = dtsgen.process(stm32_dma_v2_dts_template_h)
+
+
+# it seems that only the STM32u5 has the enhanced GPDMA
+bsp_private_gen_source_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32U5', if_true: [ stm32_gpdma_dtsgen_c, stm32_gpdma_dtsgen_h ])
 bsp_private_gen_source_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32U5', if_true: files('stm32u5-gpdma.c'))
 
+# Other STM32 families have older GPDMA implementations, being st-dma-v1 or st-dma-v2 depending on the family
+# the selection is made at soc subfamily level but the config name is unified for a more generic inclusion here
+bsp_private_gen_source_set.add(when: 'CONFIG_HAS_GPDMA_ST_DMAV1', if_true: [ stm32_dma_v1_dtsgen_c, stm32_dma_v1_dtsgen_h ])
+bsp_private_gen_source_set.add(when: 'CONFIG_HAS_GPDMA_ST_DMAV1', if_true: files('stm32-dmav1.c'))
+
+bsp_private_gen_source_set.add(when: 'CONFIG_HAS_GPDMA_ST_DMAV2', if_true: [ stm32_dma_v2_dtsgen_c, stm32_dma_v2_dtsgen_h ])
+bsp_private_gen_source_set.add(when: 'CONFIG_HAS_GPDMA_ST_DMAV2', if_true: files('stm32-dmav2.c'))
+
 # driver source selection