DMA: support for various STM32 DMA controllers#124
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Pull request overview
This PR expands Sentry’s STM32 DMA support beyond the existing STM32U5 GPDMA driver by adding DTS-generated controller descriptors and new driver implementations for STM32 “st-dma-v1” (e.g., STM32F4) and “st-dma-v2” (e.g., STM32WB / STM32L4).
Changes:
- Add new STM32 DMA v1 and v2 drivers implementing the generic
gpdma_*API. - Add DTS-to-C generation templates for STM32 DMA v1/v2 controller descriptors and hook them into the Meson build based on new Kconfig symbols.
- Update Cortex-M Kconfig selections for STM32F4/L4/WB families and add an STM32F429 example DTS fragment.
Reviewed changes
Copilot reviewed 11 out of 11 changed files in this pull request and generated 6 comments.
Show a summary per file
| File | Description |
|---|---|
| kernel/src/managers/dma/dma-dt.c.in | Extends DMA controller compatible selection to include stm32-dma-v1/v2. |
| kernel/src/drivers/dma/stm32-st-dmav2-dt.h.in | New DTS-generated descriptor header template for STM32 DMA v2. |
| kernel/src/drivers/dma/stm32-st-dmav2-dt.c.in | New DTS-generated descriptor source template for STM32 DMA v2. |
| kernel/src/drivers/dma/stm32-st-dmav1-dt.h.in | New DTS-generated descriptor header template for STM32 DMA v1. |
| kernel/src/drivers/dma/stm32-st-dmav1-dt.c.in | New DTS-generated descriptor source template for STM32 DMA v1. |
| kernel/src/drivers/dma/stm32-dmav2.c | New STM32 DMA v2 driver implementing the generic GPDMA API. |
| kernel/src/drivers/dma/stm32-dmav1.c | New STM32 DMA v1 (F4-style stream DMA) driver implementing the generic GPDMA API. |
| kernel/src/drivers/dma/meson.build | Build integration: conditional generation/compilation for U5 vs st-dma-v1/v2 variants. |
| kernel/src/arch/asm-generic/Kconfig | Adds HAS_GPDMA_ST_DMAV1 / HAS_GPDMA_ST_DMAV2 capability symbols. |
| kernel/src/arch/asm-cortex-m/Kconfig | Selects the new DMA capability symbols for STM32F4/L4/WB subfamilies. |
| dts/examples/stm32f429i_disc1_autotest.dts | Adds an example DMA stream and enables DMA1 with an owned channel. |
Comments suppressed due to low confidence (2)
kernel/src/drivers/dma/stm32-dmav1.c:118
stm32_dmav1_get_stream_raw_flags()masks with0x1F, but STM32F4 DMA stream flags occupy a 6-bit field with a reserved bit (see the0x0F7D0F7Dclear mask used instm32_dmav1_probe()). This will drop/shift bits and can misreport transfer-complete/error/half-transfer states. Update the extraction to use the correct per-stream mask/bit layout.
static inline uint32_t stm32_dmav1_get_stream_raw_flags(uint8_t stream, uint32_t isr)
{
uint32_t const shift = stm32_dma_stream_flag_shift[stream];
return (isr >> shift) & 0x1FUL;
}
kernel/src/drivers/dma/stm32-dmav1.c:131
stm32_dmav1_get_stream_clr_flags()returns(0x1F << shift), but STM32F4 DMA clears a non-contiguous set of bits per stream (reserved bit inside the 6-bit field). This means some interrupt flags may not get cleared. Use the correct per-stream clear mask (consistent with the0x0F7D0F7Dpattern used to clear all flags instm32_dmav1_probe()).
static inline uint32_t stm32_dmav1_get_stream_clr_flags(uint8_t stream)
{
uint32_t const shift = stm32_dma_stream_flag_shift[stream];
return (0x1FUL << shift);
}
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| /** @name Per-stream status bits extracted from LISR/HISR */ | ||
| /** @{ */ | ||
| #define STM32_DMA_STATUS_FLAG_FEIF (1UL << 0) | ||
| #define STM32_DMA_STATUS_FLAG_DMEIF (1UL << 1) | ||
| #define STM32_DMA_STATUS_FLAG_TEIF (1UL << 2) | ||
| #define STM32_DMA_STATUS_FLAG_HTIF (1UL << 3) | ||
| #define STM32_DMA_STATUS_FLAG_TCIF (1UL << 4) |
| * | ||
| * Descriptor is feed from device tree file | ||
| * | ||
| * \note Only node w/ compatible="st,stm32-usart" and status="okay" properties |
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| * \note Only node w/ compatible="st,stm32-usart" and status="okay" properties | ||
| * will be parsed |
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| dma-streams { | ||
| // device-to-memory DMA stream | ||
| stream1 { | ||
| compatible = "dma-stream"; | ||
| channel = <&dma1_1>; | ||
| streamid = <3>; // channel stream (af) identifier | ||
| prio = <STM32_DMA_PRIORITY_MEDIUM>; | ||
| source = <&usart1>; | ||
| dest = <&shm_autotest_1>; | ||
| length = <42>; | ||
| circular = <1 0>; // circular source, linear dest | ||
| sentry,label = <0x1>; // task-level unique DMA identifier | ||
| }; | ||
| // memory-to-memory DMA stream | ||
| stream2 { | ||
| compatible = "dma-stream"; | ||
| channel = <&dma1_1>; | ||
| streamid = <1>; // channel stream (af) identifier | ||
| prio = <STM32_DMA_PRIORITY_MEDIUM>; | ||
| source = <&shm_autotest_1>; | ||
| dest = <&shm_autotest_2>; | ||
| length = <42>; | ||
| circular = <1 0>; // circular source, linear dest | ||
| sentry,label = <0x2>; // task-level unique DMA identifier | ||
| }; | ||
| }; |
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| compatible = "dma-stream"; | ||
| channel = <&dma1_1>; | ||
| streamid = <3>; // channel stream (af) identifier | ||
| prio = <STM32_DMA_PRIORITY_MEDIUM>; | ||
| source = <&usart1>; | ||
| dest = <&shm_autotest_1>; | ||
| length = <42>; |
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| static inline bool stm32_dmav2_is_valid_desc(gpdma_stream_cfg_t const * const desc, | ||
| stm32_gpdma_desc_t const ** const ctrl) | ||
| { | ||
| if (unlikely((desc == NULL) || (ctrl == NULL))) { | ||
| return false; | ||
| } | ||
| *ctrl = stm32_gpdma_get_desc(desc->controller); | ||
| if (unlikely(*ctrl == NULL)) { | ||
| return false; | ||
| } | ||
| if (unlikely(desc->channel >= (*ctrl)->num_chan)) { | ||
| return false; | ||
| } | ||
| return true; |
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By now, only the STM32U5 GPDMA driver was supported, meaning that other ST SoCs do not have their DMA supported in Sentry.
This PR adding drivers for:
Note that this PR do not add the already unsupported gpdma_stream_unassign() support, which will be updated in another PR, but only align DMA support for various STM32 familly SoCs.
This also allows, for to-be-added SoCs such as stm32h5 to easily include ST DMA-v2 controller familly drivers.
issue: still have a memcmp() memory comparison between SHM after dma copy generating a memfault. to investigate and fix before merge.