arch/arm/src/stm32h5: Add support for USB host

Documentation/platforms/arm/stm32h5/index.rst

@@ -49,7 +49,7 @@ OCTOSPI     Yes      Implemented as QSPI.
 PWR         Yes      Partial.
 SPI         Yes
 TIM         Yes
-USB_FS      Yes      USB Device Support.
+USB_FS      Yes      USB Device and Host Support.
 
 AES         No
 CEC         No
@@ -86,6 +86,26 @@ WWDG        No
 
 ==========  =======  =====
 
+USB FS Host
+-----------
+
+STM32 USB FS Host Driver Support. The STM32H5 is equipped with a Dual Role USB device
+capable of operating as a device or host. 
+
+Pre-requisites:
+
+- CONFIG_USBHOST         - Enable USB host support
+- CONFIG_STM32H5_USBFS_HOST  - Enable the STM32 USB OTG FS block in host mode
+
+USB host requires a stable 48MHz clock. This should come from a PLL driven by the HSE.
+HSI48 cannot be reliably used in host mode due to drift. It can only be used in device mode.
+
+Options:
+
+- STM32H5_USBDRD_NCHANNELS - Number of host channels. Default 8
+
+- STM32H5_USBDRD_DESCSIZE - Maximum size of a descriptor.  Default: 128
+
 References
 =================
 [RM0481] Reference Manual: STM32H523/33xx, STM32H562/63xx, and STM32H573xx Arm® -based 32-bit MCUs

arch/arm/src/stm32h5/CMakeLists.txt

@@ -96,6 +96,10 @@ if(CONFIG_STM32H5_USBFS)
   list(APPEND SRCS stm32_usbfs.c)
 endif()
 
+if(CONFIG_STM32H5_USBFS_HOST)
+  list(APPEND SRCS stm32_usbdrdhost.c)
+endif()
+
 if(CONFIG_STM32H5_ETHMAC)
   list(APPEND SRCS stm32_ethernet.c)
 endif()

arch/arm/src/stm32h5/Kconfig

@@ -651,12 +651,30 @@ config STM32H5_TIM17
 
 endmenu # STM32H5 Timer Selection
 
+choice STM32H5_USBFS_MODE
+	prompt "USB FS Mode"
+	depends on STM32H5_HAVE_USBFS
+	default STM32H5_USBFS_NONE
+	---help---
+	  Select the operating mode for the USB_DRD_FS peripheral.
+	  The hardware supports Device or Host, but not simultaneously.
+
+config STM32H5_USBFS_NONE
+	bool "Disabled"
+
 config STM32H5_USBFS
 	bool "USB Device"
-	default n
-	depends on STM32H5_HAVE_USBFS
 	select USBDEV
 
+config STM32H5_USBFS_HOST
+	bool "USB Host"
+	select USBHOST_HAVE_ASYNCH
+	select USBHOST
+	---help---
+	  Enable USB host mode for USB_DRD_FS peripheral.
+
+endchoice
+
 endmenu # STM32H5 Peripheral Selection
 
 menu "DTS Configuration"
@@ -4473,7 +4491,7 @@ endmenu # Timer Configuration
 
 comment "USB Device Configuration"
 
-menu "USB Full Speed Debug Configuration"
+menu "USB Full Speed Device Configuration"
 	depends on STM32H5_USBFS
 
 config STM32H5_USBFS_REGDEBUG
@@ -4485,6 +4503,28 @@ config STM32H5_USBFS_REGDEBUG
 
 endmenu
 
+comment "USB Host Configuration"
+
+menu "USB Full Speed Host Configuration"
+	depends on STM32H5_USBFS_HOST
+
+config STM32H5_USBDRD_NCHANNELS
+	int "Number of host channels"
+	default 8
+	range 1 8
+	depends on STM32H5_USBFS_HOST
+	---help---
+		Number of USB host channels to use.
+
+config STM32H5_USBDRD_DESCSIZE
+	int "Descriptor buffer size"
+	default 128
+	depends on STM32H5_USBFS_HOST
+	---help---
+		Size of descriptor/request buffers.
+
+endmenu
+
 config STM32H5_SERIALDRIVER
 	bool
 

arch/arm/src/stm32h5/Make.defs

@@ -92,6 +92,10 @@ ifeq ($(CONFIG_STM32H5_USBFS),y)
 CHIP_CSRCS += stm32_usbfs.c
 endif
 
+ifeq ($(CONFIG_STM32H5_USBFS_HOST),y)
+CHIP_CSRCS += stm32_usbdrdhost.c
+endif
+
 ifeq ($(CONFIG_STM32H5_ETHMAC),y)
 CHIP_CSRCS += stm32_ethernet.c
 endif

arch/arm/src/stm32h5/hardware/stm32_usbfs.h

@@ -151,6 +151,9 @@
 #define USB_CNTR_ERRM                  (1 << 13) /* Bit 13: Error Interrupt Mask */
 #define USB_CNTR_PMAOVRN               (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
 #define USB_CNTR_CTRM                  (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
+#define USB_CNTR_THR512M               (1 << 16) /* Bit 16: 512byte Threshold interrupt mask */
+#define USB_CNTR_DDISCM                (1 << 17) /* Bit 17: Device disconnection mask */
+#define USB_CNTR_HOST                  (1 << 31) /* Bit 31: Host Mode */
 
 #define USB_CNTR_ALLINTS               (USB_CNTR_L1REQ|USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|\
                                         USB_CNTR_SUSPM|USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_PMAOVRN|\
@@ -164,12 +167,16 @@
 #define USB_ISTR_L1REQ                 (1 << 7)  /* Bit 7:  LPM L1 state request */
 #define USB_ISTR_ESOF                  (1 << 8)  /* Bit 8:  Expected Start Of Frame */
 #define USB_ISTR_SOF                   (1 << 9)  /* Bit 9:  Start Of Frame */
-#define USB_ISTR_RESET                 (1 << 10) /* Bit 10: USB RESET request */
+#define USB_ISTR_RESET                 (1 << 10) /* Bit 10: USB RESET request. Device connection in Host mode */
 #define USB_ISTR_SUSP                  (1 << 11) /* Bit 11: Suspend mode request */
 #define USB_ISTR_WKUP                  (1 << 12) /* Bit 12: Wake up */
 #define USB_ISTR_ERR                   (1 << 13) /* Bit 13: Error */
 #define USB_ISTR_PMAOVRN               (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
 #define USB_ISTR_CTR                   (1 << 15) /* Bit 15: Correct Transfer */
+#define USB_ISTR_THR512                (1 << 16) /* Bit 16: 512byte threshold interrupt */
+#define USB_ISTR_DDISC                 (1 << 17) /* Bit 17: Device disconnection */
+#define USB_ISTR_DCON_STAT             (1 << 29) /* Bit 29: Device connection status */
+#define USB_ISTR_LS_DCONN              (1 << 30) /* Bit 30: Low-speed device connected */
 
 #define USB_ISTR_ALLINTS               (USB_ISTR_L1REQ|USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|\
                                         USB_ISTR_SUSP|USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_PMAOVRN|\
@@ -210,18 +217,118 @@
 #define USB_BCDR_SDET                  (1 << 6)  /* Bit 6:  Secondary detection (SD) status */
 #define USB_BCDR_PS2DET                (1 << 7)  /* Bit 7:  DM pull-up detection status */
 #define USB_BCDR_DPPU                  (1 << 15) /* Bit 15: DP pull-up control */
+#define USB_BCDR_DPPD                  (1 << 15) /* Bit 15: DP pull-down control (host mode) */
+
+/****************************************************************************
+ * USB DRD Host Mode Register Definitions
+ ****************************************************************************/
+
+/* Channel/Endpoint register */
+
+#define USB_CHEP_ADDR_SHIFT            (0)       /* Bits 3-0: Endpoint address */
+#define USB_CHEP_ADDR_MASK             (0xf << USB_CHEP_ADDR_SHIFT)
+#define USB_CHEP_TX_STTX_SHIFT         (4)       /* Bits 5-4: Status TX */
+#define USB_CHEP_TX_STTX_MASK          (3 << USB_CHEP_TX_STTX_SHIFT)
+#  define USB_CHEP_TX_STTX_DIS         (0 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX disabled */
+#  define USB_CHEP_TX_STTX_STALL       (1 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX stalled */
+#  define USB_CHEP_TX_STTX_NAK         (2 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX NAK */
+#  define USB_CHEP_TX_STTX_VALID       (3 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX valid */
+#  define USB_CHEP_TX_DTOG1            (1 << USB_CHEP_TX_STTX_SHIFT) /* TX Data Toggle bit 1 */
+#  define USB_CHEP_TX_DTOG2            (2 << USB_CHEP_TX_STTX_SHIFT) /* TX Data Toggle bit 2 */
+
+#define USB_CHEP_DTOG_TX               (1 << 6)  /* Bit 6: Data Toggle TX */
+#define USB_CHEP_VTTX                  (1 << 7)  /* Bit 7: Valid transaction transmitted */
+#define USB_CHEP_KIND                  (1 << 8)  /* Bit 8: Endpoint/Channel KIND */
+#define USB_CHEP_UTYPE_SHIFT           (9)       /* Bits 10-9: USB type of transaction */
+#define USB_CHEP_UTYPE_MASK            (3 << USB_CHEP_UTYPE_SHIFT)
+#  define USB_CHEP_UTYPE_BULK          (0 << USB_CHEP_UTYPE_SHIFT) /* Bulk transfer */
+#  define USB_CHEP_UTYPE_CTRL          (1 << USB_CHEP_UTYPE_SHIFT) /* Control transfer */
+#  define USB_CHEP_UTYPE_ISOC          (2 << USB_CHEP_UTYPE_SHIFT) /* Isochronous transfer */
+#  define USB_CHEP_UTYPE_INTR          (3 << USB_CHEP_UTYPE_SHIFT) /* Interrupt transfer */
+
+#define USB_CHEP_SETUP                 (1 << 11) /* Bit 11: Setup transaction completed */
+#define USB_CHEP_RX_STRX_SHIFT         (12)      /* Bits 13-12: Status RX */
+#define USB_CHEP_RX_STRX_MASK          (3 << USB_CHEP_RX_STRX_SHIFT)
+#  define USB_CHEP_RX_STRX_DIS         (0 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX disabled */
+#  define USB_CHEP_RX_STRX_STALL       (1 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX stalled */
+#  define USB_CHEP_RX_STRX_NAK         (2 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX NAK */
+#  define USB_CHEP_RX_STRX_VALID       (3 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX valid */
+#  define USB_CHEP_RX_DTOG1            (1 << USB_CHEP_RX_STRX_SHIFT) /* RX Data Toggle bit 1 */
+#  define USB_CHEP_RX_DTOG2            (2 << USB_CHEP_RX_STRX_SHIFT) /* RX Data Toggle bit 2 */
+
+#define USB_CHEP_DTOG_RX               (1 << 14) /* Bit 14: Data Toggle RX */
+#define USB_CHEP_VTRX                  (1 << 15) /* Bit 15: Valid transaction received */
+#define USB_CHEP_DEVADDR_SHIFT         (16)      /* Bits 22-16: Target device address */
+#define USB_CHEP_DEVADDR_MASK          (0x7f << USB_CHEP_DEVADDR_SHIFT)
+#define USB_CHEP_NAK                   (1 << 23) /* Bit 23: Previous NAK detected */
+#define USB_CHEP_LSEP                  (1 << 24) /* Bit 24: Low Speed Endpoint */
+#define USB_CHEP_ERRTX                 (1 << 25) /* Bit 25: Transmit error */
+#define USB_CHEP_ERRRX                 (1 << 26) /* Bit 26: Receive error */
+
+/* Register mask for preserving r/w bits when modifying toggle bits */
+
+#define USB_CHEP_REG_MASK              (USB_CHEP_ERRRX | USB_CHEP_ERRTX | \
+                                        USB_CHEP_LSEP | USB_CHEP_DEVADDR_MASK | \
+                                        USB_CHEP_VTRX | USB_CHEP_SETUP | \
+                                        USB_CHEP_UTYPE_MASK | USB_CHEP_KIND | \
+                                        USB_CHEP_VTTX | USB_CHEP_ADDR_MASK | \
+                                        USB_CHEP_NAK)
+
+#define USB_CHEP_TX_DTOGMASK           (USB_CHEP_TX_STTX_MASK | USB_CHEP_REG_MASK)
+#define USB_CHEP_RX_DTOGMASK           (USB_CHEP_RX_STRX_MASK | USB_CHEP_REG_MASK)
+#define USB_CH_T_MASK                  ((~USB_CHEP_UTYPE_MASK) & USB_CHEP_REG_MASK)
+#define USB_CHEP_DB_MSK                (0xffff0f0f)
+
+/* PMA (Packet Memory Area) definitions for host mode */
+
+#define USB_DRD_PMA_SIZE               (2048)     /* 2KB PMA */
+#define USB_DRD_NCHANNELS              (8)        /* 8 host channels */
+
+/* PMA buffer descriptor structure address calculation
+ * Each channel has TX and RX buffer descriptors (8 bytes total per channel)
+ */
+
+#define USB_PMA_TXBD_OFFSET(ch)        ((ch) * 8)
+#define USB_PMA_RXBD_OFFSET(ch)        ((ch) * 8 + 4)
+
+/* PMA TX buffer descriptor bit definitions */
+
+#define USB_PMA_TXBD_ADDR_SHIFT        (2)        /* Bits 15:2: TX buffer address */
+#define USB_PMA_TXBD_ADDR_MASK         (0x3fff << USB_PMA_TXBD_ADDR_SHIFT)
+#define USB_PMA_TXBD_COUNT_SHIFT       (16)       /* Bits 25:16: TX byte count */
+#define USB_PMA_TXBD_COUNT_MASK        (0x3ff << USB_PMA_TXBD_COUNT_SHIFT)
+#define USB_PMA_TXBD_ADDMSK            (0xffff0000)
+#define USB_PMA_TXBD_COUNTMSK          (0x0000ffff)
+
+/* PMA RX buffer descriptor bit definitions */
+
+#define USB_PMA_RXBD_ADDR_SHIFT        (2)        /* Bits 15-2: RX buffer address */
+#define USB_PMA_RXBD_ADDR_MASK         (0x3fff << USB_PMA_RXBD_ADDR_SHIFT)
+#define USB_PMA_RXBD_COUNT_SHIFT       (16)       /* Bits 25-16: RX byte count */
+#define USB_PMA_RXBD_COUNT_MASK        (0x3ff << USB_PMA_RXBD_COUNT_SHIFT)
+#define USB_PMA_RXBD_NUM_BLOCK_SHIFT   (26)      /* Bits 30-26: Number of blocks */
+#define USB_PMA_RXBD_NUM_BLOCK_MASK    (0x1f << USB_PMA_RXBD_NUM_BLOCK_SHIFT)
+#define USB_PMA_RXBD_BLSIZE            (1 << 31) /* Bit 31: Block size: 0=2bytes, 1=32bytes */
+#define USB_PMA_RXBD_ADDMSK            (0xffff0000)
+
+/* PMA start address (after buffer descriptor table)
+ * BDT size = 8 channels * 8 bytes = 64 bytes, aligned to 64
+ */
+
+#define USB_DRD_PMA_BDT_SIZE           (USB_DRD_NCHANNELS * 8)
+#define USB_DRD_PMA_START_ADDR         (USB_DRD_PMA_BDT_SIZE)
 
 /* Reception buffer address */
 
-#define USB_ADDR_RX_SHIFT              (2)       /* Bits 15:2 ADDRn_RX[15:2]: Reception Buffer Address */
+#define USB_ADDR_RX_SHIFT              (2)       /* Bits 15-2: Reception Buffer Address */
 #define USB_ADDR_RX_MASK               (0x3fff << USB_ADDR_RX_SHIFT)
 
 /* Reception byte count */
 
-#define USB_COUNT_RX_BL_SIZE           (1 << 31) /* Bit 15: BLock SIZE. */
-#define USB_COUNT_RX_NUM_BLOCK_SHIFT   (26)      /* Bits 14-10: Number of blocks */
+#define USB_COUNT_RX_BL_SIZE           (1 << 31) /* Bit 31: Block size: 0=2bytes, 1=32bytes */
+#define USB_COUNT_RX_NUM_BLOCK_SHIFT   (26)      /* Bits 30-26: Number of blocks */
 #define USB_COUNT_RX_NUM_BLOCK_MASK    (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
-#define USB_COUNT_RX_SHIFT             (16)       /* Bits 9-0: Reception Byte Count */
+#define USB_COUNT_RX_SHIFT             (16)      /* Bits 25-16: Reception Byte Count */
 #define USB_COUNT_RX_MASK              (0x3ff << USB_COUNT_RX_SHIFT)
 
 #endif /* CONFIG_STM32H5_HAVE_USBFS */

arch/arm/src/stm32h5/stm32_serial.c

@@ -3745,6 +3745,7 @@ static bool stm32serial_txready(struct uart_dev_s *dev)
  *
  ****************************************************************************/
 
+#ifdef SERIAL_HAVE_DMA
 static void stm32serial_dmarxcallback(DMA_HANDLE handle,
                                       uint8_t status,
                                       void *arg)
@@ -3779,6 +3780,7 @@ static void stm32serial_dmarxcallback(DMA_HANDLE handle,
                         USART_ICR_ORECF | USART_ICR_NCF | USART_ICR_FECF);
     }
 }
+#endif
 
 /****************************************************************************
  * Name: stm32serial_pmnotify