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projects: adrd8012_01z: Change name of AD_GMSL2ETH_SL project (currently ADRD8012_01z) #2020

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docs: adrd8012_01z: Change name of AD_GMSL2ETH_SL board (currently AD…
alin724 Mar 1, 2026
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projects: adrd8012_01z: Change name of AD_GMSL2ETH_SL project (curren…
alin724 Mar 1, 2026
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0 ...ojects/ad_gmsl2eth_sl/ad_gmsl2eth_hdl.svg → ...rojects/adrd8012_01z/adrd8012_01z_hdl.svg
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18 changes: 9 additions & 9 deletions docs/projects/ad_gmsl2eth_sl/index.rst → docs/projects/adrd8012_01z/index.rst
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@@ -1,12 +1,12 @@
.. _ad_gmsl2eth_sl:
.. _adrd8012_01z:

AD-GMSL2ETH-SL HDL project
ADRD8012-01Z HDL project
===============================================================================

Overview
-------------------------------------------------------------------------------

The :adi:`AD-GMSL2ETH-SL` is an edge compute platform enabling low-latency
The :adi:`ADRD8012-01Z` is an edge compute platform enabling low-latency
data transfer from eight Gigabit Multimedia Serial Link™ (GMSL) interfaces
on to a 10 Gb Ethernet link. The target applications include autonomous robots
and vehicles where machine vision and real-time sensor fusion is critical.
Expand All @@ -27,7 +27,7 @@ and the PTP logic.
Supported boards
-------------------------------------------------------------------------------

- :adi:`AD-GMSL2ETH-SL`
- :adi:`ADRD8012-01Z`

Supported devices
-------------------------------------------------------------------------------
Expand Down Expand Up @@ -60,10 +60,10 @@ The data path designed in this reference design is as follows:

The data path and elements of the video network, 10G NIC, are depicted in the below diagram:

.. image:: ad_gmsl2eth_hdl.svg
.. image:: adrd8012_01z_hdl.svg
:width: 1200
:align: center
:alt: AD-GMSL2ETH-SL Evaluation Kit HDL-related block design
:alt: ADRD8012-01Z Evaluation Kit HDL-related block design

CPU/Memory interconnects addresses
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Expand Down Expand Up @@ -238,7 +238,7 @@ apply the indicated patch.
$cd corundum
$git checkout 37f2607
$git apply ../hdl/library/corundum/patch_axis_xgmii_rx_64.patch
$cd ../hdl/projects/ad_gmsl2eth_sl/k26
$cd ../hdl/projects/adrd8012_01z/k26
$make

A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
Expand All @@ -263,7 +263,7 @@ Hardware related

- Product datasheets:

- :adi:`AD-GMSL2ETH-SL`
- :adi:`ADRD8012-01Z`
- :adi:`MAX96724 <media/en/technical-documentation/data-sheets/max96724.pdf>`
- :adi:`MAX17573 <media/en/technical-documentation/data-sheets/max17573.pdf>`
- :adi:`ADM7154 <media/en/technical-documentation/data-sheets/adm7154.pdf>`
Expand All @@ -275,7 +275,7 @@ Hardware related
HDL related
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

- :git-hdl:`AD-GMSL2ETH-SL HDL project source code <projects/ad_gmsl2eth_sl>`
- :git-hdl:`ADRD8012-01Z HDL project source code <projects/adrd8012_01z>`

.. list-table::
:widths: 30 35 35
Expand Down
2 changes: 1 addition & 1 deletion docs/projects/index.rst
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Expand Up @@ -18,7 +18,7 @@ Contents
.. toctree::
:maxdepth: 1

AD-GMSL2ETH-SL <ad_gmsl2eth_sl/index>
ADRD8012-01Z <adrd8012_01z/index>
AD-QUADMXFE1-EBZ <ad_quadmxfe1_ebz/index>
AD353XR <ad353xr/index>
AD35XXR-EVB <ad35xxr_evb/index>
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0 projects/ad_gmsl2eth_sl/Makefile → projects/adrd8012_01z/Makefile
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6 changes: 3 additions & 3 deletions projects/ad_gmsl2eth_sl/README.md → projects/adrd8012_01z/README.md
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@@ -1,7 +1,7 @@
# AD-GMSL2ETH-SL HDL Project
# ADRD8012-01Z HDL Project

- Evaluation board product page: [AD-GMSL2ETH-SL](https://www.analog.com/ad-gmsl2eth-sl)
- System documentation: https://wiki.analog.com/resources/eval/user-guides/ad-gmsl2eth-sl-guide
- Evaluation board product page: [ADRD8012-01Z](https://www.analog.com/adrd8012-01z)
- System documentation: https://analogdevicesinc.github.io/documentation/solutions/reference-designs/adrd8012-01Z/index.html
- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad_gmsl2eth_sl/index.html

## Supported parts
Expand Down
23 changes: 4 additions & 19 deletions ..._gmsl2eth_sl/common/ad_gmsl2eth_sl_bd.tcl → ...s/adrd8012_01z/common/adrd8012_01z_bd.tcl
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2024-2026 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -461,29 +461,14 @@ ad_ip_parameter clk10_gen CONFIG.PRIM_SOURCE {Global_buffer}
ad_ip_parameter clk10_gen CONFIG.RESET_TYPE {ACTIVE_LOW}
ad_ip_parameter clk10_gen CONFIG.USE_LOCKED {false}

ad_ip_instance clk_wiz clk125_gen
ad_ip_parameter clk125_gen CONFIG.CLKIN1_UI_JITTER {0}
ad_ip_parameter clk125_gen CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE {50.000}
ad_ip_parameter clk125_gen CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}
ad_ip_parameter clk125_gen CONFIG.CLKOUT1_REQUESTED_PHASE {0.000}
ad_ip_parameter clk125_gen CONFIG.PRIMITIVE {PLL}
ad_ip_parameter clk125_gen CONFIG.PRIM_SOURCE {Global_buffer}
ad_ip_parameter clk125_gen CONFIG.RESET_TYPE {ACTIVE_LOW}
ad_ip_parameter clk125_gen CONFIG.USE_LOCKED {false}

ad_ip_instance proc_sys_reset sys_125m_rstgen
ad_connect sys_125m_rstgen/slowest_sync_clk clk125_gen/clk_out1
ad_connect sys_125m_rstgen/ext_reset_in $sys_dma_resetn

connect_bd_net [get_bd_ports led] [get_bd_pins corundum_hierarchy/ethernet_core/led]

ad_connect corundum_hierarchy/clk_corundum $sys_dma_clk
ad_connect corundum_rstgen/slowest_sync_clk $sys_dma_clk
ad_connect corundum_rstgen/ext_reset_in $sys_dma_resetn
ad_ip_parameter corundum_rstgen CONFIG.C_AUX_RESET_HIGH {0}
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@IstvanZsSzekely IstvanZsSzekely Apr 29, 2026

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I checked the latest changes, the block design, the implemented design and the discussion on the reset signals.
In the implemented design the auxiliary reset signal is hardwired to ground, the auxiliary reset's polarity is set to active low, which in theory asserts the reset and keeps the Corundum system in reset. In the Corundum creation script, the auxiliary reset's polarity is active high.
Was this design tested on hardware? I'm curious to see how this configuration behaves. As I recall, there was a similar issue with reset in a different design that might have had the same thing, where the reset was kept asserted.
This change is redundant. I recommend keeping the auxiliary reset polarity high and let Vivado hardwire it to the ground, as it won't affect the reset IP's functionality.

ad_connect corundum_rstgen/slowest_sync_clk sys_ps8/pl_clk1
ad_connect corundum_rstgen/ext_reset_in sys_ps8/pl_resetn0
ad_connect clk10_gen/clk_in1 $sys_dma_clk
ad_connect clk10_gen/resetn $sys_dma_resetn
ad_connect clk125_gen/clk_in1 $sys_dma_clk
ad_connect clk125_gen/resetn $sys_dma_resetn

ad_connect corundum_hierarchy/sfp_rx_p sfp_rx_p
ad_connect corundum_hierarchy/sfp_rx_n sfp_rx_n
Expand Down
7 changes: 3 additions & 4 deletions projects/ad_gmsl2eth_sl/k26/Makefile → projects/adrd8012_01z/k26/Makefile
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@@ -1,12 +1,12 @@
####################################################################################
## Copyright (c) 2024-2025 Analog Devices, Inc.
## Copyright (c) 2024-2026 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################

PROJECT_NAME := ad_gmsl2eth_sl_k26
PROJECT_NAME := adrd8012_01z_k26

M_DEPS += ../common/ad_gmsl2eth_sl_bd.tcl
M_DEPS += ../common/adrd8012_01z_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
Expand All @@ -15,7 +15,6 @@ M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/corundum/scripts/corundum_k26_cfg.tcl
M_DEPS += ../../../library/corundum/scripts/corundum.tcl


EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/rb_drp.tcl
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
Expand Down
2 changes: 1 addition & 1 deletion projects/ad_gmsl2eth_sl/k26/README.md → projects/adrd8012_01z/k26/README.md
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@@ -1,6 +1,6 @@
<!-- no_build_example, no_dts, no_no_os -->

# AD-GMSL2ETH-SL/K26 HDL Project
# ADRD8012-01Z/K26 HDL Project

The +VCC_SOM voltage is 5V and the SOM connectors voltages can be found in the table below:

Expand Down
4 changes: 2 additions & 2 deletions projects/ad_gmsl2eth_sl/k26/system_bd.tcl → projects/adrd8012_01z/k26/system_bd.tcl
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@@ -1,11 +1,11 @@
###############################################################################
## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2024-2026 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# Use the same base project as KV260
source ../../common/kv260/kv260_system_bd.tcl
source ../common/ad_gmsl2eth_sl_bd.tcl
source ../common/adrd8012_01z_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl

#system ID
Expand Down
0 ...ects/ad_gmsl2eth_sl/k26/system_constr.xdc → projects/adrd8012_01z/k26/system_constr.xdc
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8 changes: 4 additions & 4 deletions ...cts/ad_gmsl2eth_sl/k26/system_project.tcl → projects/adrd8012_01z/k26/system_project.tcl
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2024-2026 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand All @@ -8,8 +8,8 @@ source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl

adi_project ad_gmsl2eth_sl_k26
adi_project_files ad_gmsl2eth_sl_k26 [list \
adi_project adrd8012_01z_k26
adi_project_files adrd8012_01z_k26 [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl" \
Expand All @@ -25,4 +25,4 @@ adi_project_files ad_gmsl2eth_sl_k26 [list \
"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/tdma_ber_ch.tcl" \
"$ad_hdl_dir/library/common/ad_iobuf.v" ]

adi_project_run ad_gmsl2eth_sl_k26
adi_project_run adrd8012_01z_k26
2 changes: 1 addition & 1 deletion projects/ad_gmsl2eth_sl/k26/system_top.v → projects/adrd8012_01z/k26/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2024-2026 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down
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