projects: adrd8012_01z: Change name of AD_GMSL2ETH_SL project (currently ADRD8012_01z)#2020
projects: adrd8012_01z: Change name of AD_GMSL2ETH_SL project (currently ADRD8012_01z)#2020alin724 wants to merge 2 commits into
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…RD8012_01z) Signed-off-by: alin724 <alin-tudor.sferle@analog.com>
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…tly ADRD8012_01z) Change the name of AD_GMSL2ETH_SL HDL project + fix the Corundum NIC reset mismatch Signed-off-by: alin724 <alin-tudor.sferle@analog.com>
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| ad_connect corundum_hierarchy/clk_corundum $sys_dma_clk | ||
| ad_connect corundum_rstgen/slowest_sync_clk $sys_dma_clk | ||
| ad_connect corundum_rstgen/ext_reset_in $sys_dma_resetn | ||
| ad_ip_parameter corundum_rstgen CONFIG.C_AUX_RESET_HIGH {0} |
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I checked the latest changes, the block design, the implemented design and the discussion on the reset signals.
In the implemented design the auxiliary reset signal is hardwired to ground, the auxiliary reset's polarity is set to active low, which in theory asserts the reset and keeps the Corundum system in reset. In the Corundum creation script, the auxiliary reset's polarity is active high.
Was this design tested on hardware? I'm curious to see how this configuration behaves. As I recall, there was a similar issue with reset in a different design that might have had the same thing, where the reset was kept asserted.
This change is redundant. I recommend keeping the auxiliary reset polarity high and let Vivado hardwire it to the ground, as it won't affect the reset IP's functionality.
PR Description
Change name of AD_GMSL2ETH_SL project (currently ADRD8012_01z)
PR Type
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