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| .. _ad5706r: | ||
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| AD5706R HDL project | ||
| ================================================================================ | ||
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| Overview | ||
| -------------------------------------------------------------------------------- | ||
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| The :adi:`AD5706R` devices are 4-channel, 16-/12-/10-bit resolution, low noise, | ||
| programmable current output, digital-to-analog converter (DAC) capable of | ||
| multiple operating modes and output current ranges with high power efficiency. | ||
| These are intended for photonics control and current mode biasing applications. | ||
| The devices incorporate a 2.5V, on-chip voltage reference, die temperature, load | ||
| DAC, and A/B toggle functions, output monitoring functions, and reset functions. | ||
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| The family provides multiple programmable output current ranges up to 300mA. | ||
| With device addressable pins, an SPI transaction can communicate with up to four | ||
| :adi:`AD5706R` on the same SPI bus. Each DAC operates with an independent | ||
| positive power supply rails PVDDx from 1.65V to 3.6V, for optimizing power | ||
| efficiency and thermal power dissipation. The AD5706R operate from a 2.9V to | ||
| 3.6V AVDD supply and are specified over the −40°C to +125°C temperature range. | ||
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| Applications: | ||
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| - Photonics Control | ||
| - Optical Communications | ||
| - LED Driver Programmable Current Source | ||
| - Current Mode Biasing | ||
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| Supported boards | ||
| ------------------------------------------------------------------------------- | ||
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| - :adi:`EVAL-AD5706RARDZ` | ||
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| Supported devices | ||
| ------------------------------------------------------------------------------- | ||
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| - :adi:`AD5706` | ||
| - :adi:`AD5706R` | ||
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| Supported carriers | ||
| ------------------------------------------------------------------------------- | ||
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| - :xilinx:`Cora Z7-07S <products/boards-and-kits/1-1qlaz7n.html>` on Arduino Header | ||
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| Block design | ||
| ------------------------------------------------------------------------------- | ||
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| Block diagram | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| The data path is depicted in the below diagram: | ||
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| .. image:: ad5706r_block_diagram.svg | ||
| :width: 800 | ||
| :align: center | ||
| :alt: AD5706R block diagram | ||
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| Hardware setup | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| ========= ================= ============= | ||
| Signal AD5706R Testpoint Cora Z7s | ||
| ========= ================= ============= | ||
| SPI_CSB CS CHIPKIT IO 10 | ||
| SPI_SDO SDO CHIPKIT IO 11 | ||
| SPI_SDI SDI CHIPKIT IO 12 | ||
| SPI_SCLK SCK CHIPKIT IO 13 | ||
| SHDN PMOD P7 CHIPKIT IO 7 | ||
| RESETB RESET CHIPKIT IO 8 | ||
| LDACB_TGP PMOD P6 CHIPKIT IO 9 | ||
| ========= ================= ============= | ||
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| .. important:: | ||
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| The evaluation board is powered by 5 V voltage from an external USB. | ||
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| CPU/Memory interconnects addresses | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| The addresses are dependent on the architecture of the FPGA, having an offset | ||
| added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). | ||
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| =================== ========== | ||
| Instance Zynq | ||
| =================== ========== | ||
| axi_ad5706R_pwm_gen 0x44A00000 | ||
| xadc_in 0x44A50000 | ||
| =================== ========== | ||
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| GPIOs | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| The Software GPIO number is calculated as follows: | ||
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| - Zynq-7000: if PS7 is used, then the offset is 54 | ||
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| .. list-table:: | ||
| :widths: 25 25 25 25 | ||
| :header-rows: 2 | ||
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| * - GPIO signal | ||
| - Direction | ||
| - HDL GPIO EMIO | ||
| - Software GPIO | ||
| * - | ||
| - (from FPGA view) | ||
| - | ||
| - Zynq-7000 | ||
| * - RESETB | ||
| - OUT | ||
| - 32 | ||
| - 86 | ||
| * - SHDN | ||
| - OUT | ||
| - 33 | ||
| - 87 | ||
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| Building the HDL project | ||
| ------------------------------------------------------------------------------- | ||
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| The design is built upon ADI's generic HDL reference design framework. | ||
| ADI distributes the bit/elf files of these projects as part of the | ||
| :external+documentation:ref:`kuiper`. | ||
| If you want to build the sources, ADI makes them available on the | ||
| :git-hdl:`HDL repository </>`. To get the source you must | ||
| `clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__ | ||
| the HDL repository, and then build the project as follows: | ||
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| **Linux/Cygwin/WSL** | ||
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| .. shell:: | ||
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| $cd hdl/projects/ad5706r/coraz7s | ||
| $make | ||
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| A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. | ||
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| Resources | ||
| ------------------------------------------------------------------------------- | ||
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| Hardware related | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| - Product datasheet: :adi:`AD5706R` | ||
| - :adi:`EVAL-AD5706R User Guide <media/en/technical-documentation/user-guides/eval-ad5706r-ardz.pdf>` | ||
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| HDL related | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| - :git-hdl:`AD5706R HDL project source code <projects/ad5706r>` | ||
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| .. list-table:: | ||
| :widths: 30 35 35 | ||
| :header-rows: 1 | ||
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| * - IP name | ||
| - Source code link | ||
| - Documentation link | ||
| * - AXI_HDMI_TX | ||
| - :git-hdl:`library/axi_hdmi_tx` | ||
| - :ref:`axi_hdmi_tx` | ||
| * - AXI_PWM_GEN | ||
| - :git-hdl:`library/axi_pwm_gen` | ||
| - :ref:`axi_pwm_gen` | ||
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| Software related | ||
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| - :git-no-os:`AD5706R No-OS project source code <projects/ad5706r>` | ||
| - :git-no-os:`AD5706R No-OS Driver source code <drivers/afe/ad5706r>` | ||
| - :git-linux:`AD5706R Linux Driver source code <drivers/iio/dac/ad5706r>` | ||
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| .. include:: ../common/more_information.rst | ||
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| .. include:: ../common/support.rst |
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| #################################################################################### | ||
| ## Copyright (c) 2025 Analog Devices, Inc. | ||
| ### SPDX short identifier: BSD-1-Clause | ||
| ## Auto-generated, do not modify! | ||
| #################################################################################### | ||
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| include ../scripts/project-toplevel.mk |
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| # AD5706R HDL Project | ||
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| - Evaluation board product page: [EVAL-AD5706RARDZ](https://analog.com/eval-ad5706r) | ||
| - System documentation: https://wiki.analog.com/resources/eval/user-guides/ad5706r | ||
| - HDL project documentation: http://analogdevicesinc.github.io/hdl/projects/ad5706r/index.html | ||
| - Evaluation board VADJ: 2.5V | ||
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| ## Supported parts | ||
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| | Part name | Description | | ||
| |-----------------------------------------------|---------------------------------------| | ||
| | [AD5706R](https://www.analog.com/AD5706R) | 4-channel, 16-bit, current output DAC | | ||
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| ## Building the project | ||
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| Please enter the folder for the FPGA carrier you want to use and read the README.md. |
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| ############################################################################### | ||
| ## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
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| create_bd_port -dir O ldacb_tgp | ||
| create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux1 | ||
| create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 spi | ||
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| # pwm gen | ||
| ad_ip_instance axi_pwm_gen axi_ad5706r_pwm_gen | ||
| ad_ip_parameter axi_ad5706r_pwm_gen CONFIG.ASYNC_CLK_EN 1 | ||
| ad_ip_parameter axi_ad5706r_pwm_gen CONFIG.PULSE_0_WIDTH 5 | ||
| ad_ip_parameter axi_ad5706r_pwm_gen CONFIG.PULSE_0_PERIOD 10 | ||
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| ad_connect axi_ad5706r_pwm_gen/pwm_0 ldacb_tgp | ||
| ad_connect axi_ad5706r_pwm_gen/ext_clk $sys_cpu_clk | ||
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| # Xilinx's XADC | ||
| ad_ip_instance xadc_wiz xadc_in | ||
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| ad_ip_parameter xadc_in CONFIG.TIMING_MODE Continuous | ||
| ad_ip_parameter xadc_in CONFIG.XADC_STARUP_SELECTION channel_sequencer | ||
| ad_ip_parameter xadc_in CONFIG.SEQUENCER_MODE Continuous | ||
| ad_ip_parameter xadc_in CONFIG.ENABLE_VCCDDRO_ALARM false | ||
| ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPAUX_ALARM false | ||
| ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPINT_ALARM false | ||
| ad_ip_parameter xadc_in CONFIG.ENABLE_AXI4STREAM false | ||
| ad_ip_parameter xadc_in CONFIG.ENABLE_EXTERNAL_MUX false | ||
| ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VP_VN false | ||
| ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 true | ||
| ad_ip_parameter xadc_in CONFIG.OT_ALARM false | ||
| ad_ip_parameter xadc_in CONFIG.SINGLE_CHANNEL_SELECTION TEMPERATURE | ||
| ad_ip_parameter xadc_in CONFIG.USER_TEMP_ALARM false | ||
| ad_ip_parameter xadc_in CONFIG.VCCAUX_ALARM false | ||
| ad_ip_parameter xadc_in CONFIG.VCCINT_ALARM false | ||
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| ad_connect xadc_in/Vaux1 xadc_vaux1 | ||
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| # interconnects (cpu) | ||
| ad_cpu_interconnect 0x44a00000 axi_ad5706r_pwm_gen | ||
| ad_cpu_interconnect 0x44a50000 xadc_in |
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| #################################################################################### | ||
| ## Copyright (c) 2025 Analog Devices, Inc. | ||
| ### SPDX short identifier: BSD-1-Clause | ||
| ## Auto-generated, do not modify! | ||
| #################################################################################### | ||
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| PROJECT_NAME := ad5706r_coraz7s | ||
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| M_DEPS += ../common/ad5706r_bd.tcl | ||
| M_DEPS += ../../scripts/adi_pd.tcl | ||
| M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl | ||
| M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc | ||
| M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl | ||
| M_DEPS += ../../../library/common/ad_iobuf.v | ||
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| LIB_DEPS += axi_sysid | ||
| LIB_DEPS += axi_pwm_gen | ||
| LIB_DEPS += sysid_rom | ||
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| include ../../scripts/project-xilinx.mk |
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| <!-- no_build_example, no_dts, no_no_os --> | ||
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| # AD5706R/CORAZ7S HDL Project | ||
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| ## Building the project | ||
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| ``` | ||
| cd projects/ad5706r/coraz7s | ||
| make | ||
| ``` |
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| ############################################################################### | ||
| ## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
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| source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl | ||
| source $ad_hdl_dir/projects/scripts/adi_pd.tcl | ||
| source ../common/ad5706r_bd.tcl | ||
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| #system ID | ||
| ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 | ||
| ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" | ||
| ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 | ||
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| sysid_gen_sys_init_file | ||
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| set sys_dma_clk [get_bd_nets sys_dma_clk] |
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| ############################################################################### | ||
| ## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
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| create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] | ||
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| # DAC SPI interface | ||
| set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { spi_csb }] ; #IO_L11N_T1_SRCC_34 Sch=ck_io[10] | ||
| set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { spi_sdo }] ; #IO_L12N_T1_MRCC_35 Sch=ck_io[11] | ||
| set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { spi_sdi }] ; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12] | ||
| set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { spi_sclk }] ; #IO_L19N_T3_VREF_35 Sch=ck_io[13] | ||
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| # DAC GPIO interface | ||
| set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { shdn }] ; #IO_L6N_T0_VREF_34 Sch=ck_io[7] | ||
| set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { resetb }] ; #IO_L13P_T2_MRCC_34 Sch=ck_io[8] | ||
| set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ldacb_tgp }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9] | ||
|
|
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| ############################################################################### | ||
| ## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. | ||
| ### SPDX short identifier: ADIBSD | ||
| ############################################################################### | ||
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| source ../../../scripts/adi_env.tcl | ||
| source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl | ||
| source $ad_hdl_dir/projects/scripts/adi_board.tcl | ||
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| adi_project ad5706r_coraz7s | ||
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| adi_project_files ad5706r_coraz7s [list \ | ||
| "$ad_hdl_dir/library/common/ad_iobuf.v" \ | ||
| "system_top.v" \ | ||
| "system_constr.xdc" \ | ||
| "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"] | ||
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| set_property PROCESSING_ORDER LATE [get_files system_constr.xdc] | ||
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| adi_project_run ad5706r_coraz7s |
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add this line to fix critical warning generated by unconnected input