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1,765 changes: 1,765 additions & 0 deletions docs/projects/ad5706r/ad5706r_block_diagram.svg
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176 changes: 176 additions & 0 deletions docs/projects/ad5706r/index.rst
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.. _ad5706r:

AD5706R HDL project
================================================================================

Overview
--------------------------------------------------------------------------------

The :adi:`AD5706R` devices are 4-channel, 16-/12-/10-bit resolution, low noise,
programmable current output, digital-to-analog converter (DAC) capable of
multiple operating modes and output current ranges with high power efficiency.
These are intended for photonics control and current mode biasing applications.
The devices incorporate a 2.5V, on-chip voltage reference, die temperature, load
DAC, and A/B toggle functions, output monitoring functions, and reset functions.

The family provides multiple programmable output current ranges up to 300mA.
With device addressable pins, an SPI transaction can communicate with up to four
:adi:`AD5706R` on the same SPI bus. Each DAC operates with an independent
positive power supply rails PVDDx from 1.65V to 3.6V, for optimizing power
efficiency and thermal power dissipation. The AD5706R operate from a 2.9V to
3.6V AVDD supply and are specified over the −40°C to +125°C temperature range.

Applications:

- Photonics Control
- Optical Communications
- LED Driver Programmable Current Source
- Current Mode Biasing

Supported boards
-------------------------------------------------------------------------------

- :adi:`EVAL-AD5706RARDZ`

Supported devices
-------------------------------------------------------------------------------

- :adi:`AD5706`
- :adi:`AD5706R`

Supported carriers
-------------------------------------------------------------------------------

- :xilinx:`Cora Z7-07S <products/boards-and-kits/1-1qlaz7n.html>` on Arduino Header

Block design
-------------------------------------------------------------------------------

Block diagram
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The data path is depicted in the below diagram:

.. image:: ad5706r_block_diagram.svg
:width: 800
:align: center
:alt: AD5706R block diagram

Hardware setup
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

========= ================= =============
Signal AD5706R Testpoint Cora Z7s
========= ================= =============
SPI_CSB CS CHIPKIT IO 10
SPI_SDO SDO CHIPKIT IO 11
SPI_SDI SDI CHIPKIT IO 12
SPI_SCLK SCK CHIPKIT IO 13
SHDN PMOD P7 CHIPKIT IO 7
RESETB RESET CHIPKIT IO 8
LDACB_TGP PMOD P6 CHIPKIT IO 9
========= ================= =============

.. important::

The evaluation board is powered by 5 V voltage from an external USB.

CPU/Memory interconnects addresses
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The addresses are dependent on the architecture of the FPGA, having an offset
added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`).

=================== ==========
Instance Zynq
=================== ==========
axi_ad5706R_pwm_gen 0x44A00000
xadc_in 0x44A50000
=================== ==========

GPIOs
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The Software GPIO number is calculated as follows:

- Zynq-7000: if PS7 is used, then the offset is 54

.. list-table::
:widths: 25 25 25 25
:header-rows: 2

* - GPIO signal
- Direction
- HDL GPIO EMIO
- Software GPIO
* -
- (from FPGA view)
-
- Zynq-7000
* - RESETB
- OUT
- 32
- 86
* - SHDN
- OUT
- 33
- 87

Building the HDL project
-------------------------------------------------------------------------------

The design is built upon ADI's generic HDL reference design framework.
ADI distributes the bit/elf files of these projects as part of the
:external+documentation:ref:`kuiper`.
If you want to build the sources, ADI makes them available on the
:git-hdl:`HDL repository </>`. To get the source you must
`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
the HDL repository, and then build the project as follows:

**Linux/Cygwin/WSL**

.. shell::

$cd hdl/projects/ad5706r/coraz7s
$make

A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.

Resources
-------------------------------------------------------------------------------

Hardware related
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

- Product datasheet: :adi:`AD5706R`
- :adi:`EVAL-AD5706R User Guide <media/en/technical-documentation/user-guides/eval-ad5706r-ardz.pdf>`

HDL related
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

- :git-hdl:`AD5706R HDL project source code <projects/ad5706r>`

.. list-table::
:widths: 30 35 35
:header-rows: 1

* - IP name
- Source code link
- Documentation link
* - AXI_HDMI_TX
- :git-hdl:`library/axi_hdmi_tx`
- :ref:`axi_hdmi_tx`
* - AXI_PWM_GEN
- :git-hdl:`library/axi_pwm_gen`
- :ref:`axi_pwm_gen`

Software related
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

- :git-no-os:`AD5706R No-OS project source code <projects/ad5706r>`
- :git-no-os:`AD5706R No-OS Driver source code <drivers/afe/ad5706r>`
- :git-linux:`AD5706R Linux Driver source code <drivers/iio/dac/ad5706r>`

.. include:: ../common/more_information.rst

.. include:: ../common/support.rst
1 change: 1 addition & 0 deletions docs/projects/index.rst
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Expand Up @@ -33,6 +33,7 @@ Contents
AD469X-EVB <ad469x_evb/index>
AD485X-FMCZ <ad485x_fmcz/index>
AD4880-FMC-EVB <ad4880_fmc_evb/index>
AD5706R <ad5706r/index>
AD5758-SDZ <ad5758_sdz/index>
AD5766-SDZ <ad5766_sdz/index>
AD57XX-ARDZ <ad57xx_ardz/index>
Expand Down
7 changes: 7 additions & 0 deletions projects/ad5706r/Makefile
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####################################################################################
## Copyright (c) 2025 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################

include ../scripts/project-toplevel.mk
16 changes: 16 additions & 0 deletions projects/ad5706r/README.md
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# AD5706R HDL Project

- Evaluation board product page: [EVAL-AD5706RARDZ](https://analog.com/eval-ad5706r)
- System documentation: https://wiki.analog.com/resources/eval/user-guides/ad5706r
- HDL project documentation: http://analogdevicesinc.github.io/hdl/projects/ad5706r/index.html
- Evaluation board VADJ: 2.5V

## Supported parts

| Part name | Description |
|-----------------------------------------------|---------------------------------------|
| [AD5706R](https://www.analog.com/AD5706R) | 4-channel, 16-bit, current output DAC |

## Building the project

Please enter the folder for the FPGA carrier you want to use and read the README.md.
42 changes: 42 additions & 0 deletions projects/ad5706r/common/ad5706r_bd.tcl
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add this line to fix critical warning generated by unconnected input

ad_connect $hier_spi_engine/trigger GND

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###############################################################################
## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

create_bd_port -dir O ldacb_tgp
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux1
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 spi

# pwm gen
ad_ip_instance axi_pwm_gen axi_ad5706r_pwm_gen
ad_ip_parameter axi_ad5706r_pwm_gen CONFIG.ASYNC_CLK_EN 1
ad_ip_parameter axi_ad5706r_pwm_gen CONFIG.PULSE_0_WIDTH 5
ad_ip_parameter axi_ad5706r_pwm_gen CONFIG.PULSE_0_PERIOD 10

ad_connect axi_ad5706r_pwm_gen/pwm_0 ldacb_tgp
ad_connect axi_ad5706r_pwm_gen/ext_clk $sys_cpu_clk

# Xilinx's XADC
ad_ip_instance xadc_wiz xadc_in

ad_ip_parameter xadc_in CONFIG.TIMING_MODE Continuous
ad_ip_parameter xadc_in CONFIG.XADC_STARUP_SELECTION channel_sequencer
ad_ip_parameter xadc_in CONFIG.SEQUENCER_MODE Continuous
ad_ip_parameter xadc_in CONFIG.ENABLE_VCCDDRO_ALARM false
ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPAUX_ALARM false
ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPINT_ALARM false
ad_ip_parameter xadc_in CONFIG.ENABLE_AXI4STREAM false
ad_ip_parameter xadc_in CONFIG.ENABLE_EXTERNAL_MUX false
ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VP_VN false
ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 true
ad_ip_parameter xadc_in CONFIG.OT_ALARM false
ad_ip_parameter xadc_in CONFIG.SINGLE_CHANNEL_SELECTION TEMPERATURE
ad_ip_parameter xadc_in CONFIG.USER_TEMP_ALARM false
ad_ip_parameter xadc_in CONFIG.VCCAUX_ALARM false
ad_ip_parameter xadc_in CONFIG.VCCINT_ALARM false

ad_connect xadc_in/Vaux1 xadc_vaux1

# interconnects (cpu)
ad_cpu_interconnect 0x44a00000 axi_ad5706r_pwm_gen
ad_cpu_interconnect 0x44a50000 xadc_in
20 changes: 20 additions & 0 deletions projects/ad5706r/coraz7s/Makefile
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####################################################################################
## Copyright (c) 2025 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################

PROJECT_NAME := ad5706r_coraz7s

M_DEPS += ../common/ad5706r_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
M_DEPS += ../../../library/common/ad_iobuf.v

LIB_DEPS += axi_sysid
LIB_DEPS += axi_pwm_gen
LIB_DEPS += sysid_rom

include ../../scripts/project-xilinx.mk
10 changes: 10 additions & 0 deletions projects/ad5706r/coraz7s/README.md
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<!-- no_build_example, no_dts, no_no_os -->

# AD5706R/CORAZ7S HDL Project

## Building the project

```
cd projects/ad5706r/coraz7s
make
```
17 changes: 17 additions & 0 deletions projects/ad5706r/coraz7s/system_bd.tcl
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###############################################################################
## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
source ../common/ad5706r_bd.tcl

#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9

sysid_gen_sys_init_file

set sys_dma_clk [get_bd_nets sys_dma_clk]
18 changes: 18 additions & 0 deletions projects/ad5706r/coraz7s/system_constr.xdc
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###############################################################################
## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]

# DAC SPI interface
set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { spi_csb }] ; #IO_L11N_T1_SRCC_34 Sch=ck_io[10]
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { spi_sdo }] ; #IO_L12N_T1_MRCC_35 Sch=ck_io[11]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { spi_sdi }] ; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { spi_sclk }] ; #IO_L19N_T3_VREF_35 Sch=ck_io[13]

# DAC GPIO interface
set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { shdn }] ; #IO_L6N_T0_VREF_34 Sch=ck_io[7]
set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { resetb }] ; #IO_L13P_T2_MRCC_34 Sch=ck_io[8]
set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ldacb_tgp }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9]

20 changes: 20 additions & 0 deletions projects/ad5706r/coraz7s/system_project.tcl
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###############################################################################
## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl

adi_project ad5706r_coraz7s

adi_project_files ad5706r_coraz7s [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]

set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]

adi_project_run ad5706r_coraz7s
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