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| \# AD5706R HDL Project | |||
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the file is oddly formatted
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| The design is built upon ADI's generic HDL reference design framework. | ||
| ADI distributes the bit/elf files of these projects as part of the | ||
| :dokuwiki:`ADI Kuiper Linux <resources/tools-software/linux-software/kuiper-linux>`. |
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:external+adi-kuiper-gen:doc:`index`
no?
@mlradu What should devs link now-a-days?
or at lease
:external+documentation:ref:`kuiper`
for a generic landing page
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edited to :external+documentation:ref:kuiper
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| - Product datasheet: :adi:`AD5706R` | ||
| - `EVAL-AD5706R User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad5706r-ardz.pdf>`__ |
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| - `EVAL-AD5706R User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad5706r-ardz.pdf>`__ | |
| - :adi:`EVAL-AD5706R User Guide <media/en/technical-documentation/user-guides/eval-ad5706r-ardz.pdf>` |
To have the adi branding in the link
| axi_ad5706R_pwm_gen 0x44A00000 | ||
| xadc_in 0x44a50000 | ||
| spi_ad5706r_dac 0x44b00000 | ||
| spi_clkgen 0x44c00000 | ||
| spi_engine_pwm_gen 0x44d00000 | ||
| spi_engine_dma 0x44e00000 |
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upper case the addresses
| added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). | ||
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| =================== ========== | ||
| Instance Zynq-7000 |
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Normally we use Zynq
Pro tip: you can navigate to an anchor
https://analogdevicesinc.github.io/hdl/projects/ad9081_fmca_ebz_x_band/index.html#cpu-memory-interconnects-addresses
Then use
Ctrl+Shift+alt+RightArrow (or Ctrl+Shift+alt+L) to navigate to the next page at the same anchor, so it is fast/easy to compare patterns.
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edited
and woah cool feature haha
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
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| ========= ================= ============= | ||
| Signal AD5706R Testpoint Cora Z7-07S |
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Normally we use Cora Z7s
| - :git-no-os:`AD5706R No-OS project source code <projects/ad5706r>` | ||
| - :git-no-os:`AD5706R No-OS Driver source code <drivers/afe/ad5706r>` | ||
| - :git-linux:`AD5706R Linux Driver source code <drivers/iio/dac/ad5706r>` | ||
| - :dokuwiki:`AD5706R No-OS Driver documentation <resources/tools-software/uc-drivers/ad5706r>` |
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This page does not exist
https://wiki.analog.com/resources/tools-software/uc-drivers/ad5706r
| - :git-no-os:`AD5706R No-OS Driver source code <drivers/afe/ad5706r>` | ||
| - :git-linux:`AD5706R Linux Driver source code <drivers/iio/dac/ad5706r>` | ||
| - :dokuwiki:`AD5706R No-OS Driver documentation <resources/tools-software/uc-drivers/ad5706r>` | ||
| - :dokuwiki:`AD5706R IIO Application <resources/tools-software/product-support-software/ad5706r_mbed_iio_application>` |
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this page does not exist
https://wiki.analog.com/resources/tools-software/product-support-software/ad5706r_mbed_iio_application
for both create at /documentation, please
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i actually thought this was ok to be placeholders
i actually am not familiar with mbed/iio and no-os so i can't create their docs
will just delete these, i've been told the wiki isn't as important as the github docu too
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| ad_ip_instance axi_clkgen spi_clkgen | ||
| ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 1 | ||
| ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 10 | ||
| ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 1 |
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spi_clkgen is set to output 10MHz which seems wrong. It should be configured to output the maximum frequency intended to be used by the design - usually 2x the max SPI SCLK frequency.
also check the parameter validity since not all combinations are valid. vivado will throw out a critical warning when they are not. right now you have the following:
[DRC AVAL-46] v7v8_mmcm_fvco_rule1: The current computed target frequency, FVCO, is out of range for cell i_system_wrapper/system_i/spi_clkgen/inst/i_mmcm_drp/i_mmcm. The computed FVCO is 50.000 MHz. The valid FVCO range for speed grade -1 is 600MHz to 1200MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 5.000, CLKIN1_PERIOD = 10.00000, and DIVCLK_DIVIDE = 10 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)).
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changed and patterned to other SPI engine projects, basically VCO_MUL 8 and CLK0DIV 5 for 160 MHz setup
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clkgen issue is still present in latest commit
| - Evaluation board product page: | ||
| - [EVAL-AD5706RARDZ](https://analog.com/eval-ad5706r) |
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| - Evaluation board product page: | |
| - [EVAL-AD5706RARDZ](https://analog.com/eval-ad5706r) | |
| - Evaluation board product page: [EVAL-AD5706RARDZ](https://analog.com/eval-ad5706r) |
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Since there is only one supported evaluation board, there's no need to create a bullet point list.
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add this line to fix critical warning generated by unconnected input
ad_connect $hier_spi_engine/trigger GND
| ad_ip_instance axi_clkgen spi_clkgen | ||
| ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 1 | ||
| ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 10 | ||
| ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 1 |
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clkgen issue is still present in latest commit
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The AD5706R devices are 4-channel, 16-/12-/10-bit resolution, low noise, programmable current output, digital-to-analog converter (DAC) capable of multiple operating modes and output current ranges with high power efficiency. The family provides multiple programmable output current ranges up to 300mA. Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
The AD5706R devices are 4-channel, 16-/12-/10-bit resolution, low noise, programmable current output, digital-to-analog converter (DAC) capable of multiple operating modes and output current ranges with high power efficiency. The family provides multiple programmable output current ranges up to 300mA. Signed-off-by: Alexis Czezar Torreno <alexisczezar.torreno@analog.com>
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v4:
This change is to reflect the linux driver and the discussed requirements that makes this |
PR Description
The AD5706R devices are 4-channel, 16-/12-/10-bit resolution, low noise,
programmable current output, digital-to-analog converter (DAC) capable of
multiple operating modes and output current ranges with high power efficiency.
The family provides multiple programmable output current ranges up to 300mA.
The project uses SPI engine to reach 50MHz transactions on CoraZ7S FPGA.
PR Type
PR Checklist