signorm: directed RTLIL, incremental optimization

backends/aiger/aiger.cc

@@ -337,7 +337,7 @@ struct AigerWriter
 				continue;
 			}
 
-			if (cell->type == ID($scopeinfo))
+			if (cell->type == ID($scopeinfo) || cell->type == ID($input_port))
 				continue;
 
 			log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));

backends/cxxrtl/cxxrtl_backend.cc

@@ -1518,6 +1518,7 @@ struct CxxrtlWorker {
 				f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
 			}
 		// Internal cells
+		} else if (cell->type == ID($input_port)) {
 		} else if (is_internal_cell(cell->type)) {
 			log_cmd_error("Unsupported internal cell `%s'.\n", cell->type);
 		// User cells

frontends/aiger/aigerparse.cc

@@ -1049,6 +1049,9 @@ struct AigerFrontend : public Frontend {
 		}
 		extra_args(f, filename, args, argidx, true);
 
+		// TODO Disabled signorm because swap_names breaks fanout logic
+		design->sigNormalize(false);
+
 		if (module_name.empty()) {
 #ifdef _WIN32
 			char fname[_MAX_FNAME];

kernel/driver.cc

@@ -725,6 +725,10 @@ int main(int argc, char **argv)
 			total_ns += gc_ns;
 			timedat.insert(make_tuple(gc_ns,
 					RTLIL::OwningIdString::garbage_collection_count(), "id_gc"));
+			total_ns += signorm_ns;
+			timedat.insert(make_tuple(signorm_ns, signorm_count, "signorm"));
+			total_ns += signorm_restore_ns;
+			timedat.insert(make_tuple(signorm_restore_ns, signorm_restore_count, "signorm_restore"));
 		}
 
 		if (timing_details)

kernel/ff.cc

@@ -635,8 +635,6 @@ Cell *FfData::emit() {
 			return nullptr;
 		}
 	}
-	if (initvals && !is_anyinit)
-		initvals->set_init(sig_q, val_init);
 	if (!is_fine) {
 		if (has_gclk) {
 			log_assert(!has_clk);
@@ -747,6 +745,8 @@ Cell *FfData::emit() {
 		}
 	}
 	cell->attributes = attributes;
+	if (initvals && !is_anyinit)
+		initvals->set_init(cell->getPort(ID::Q), val_init);
 	return cell;
 }
 

kernel/ff.h

@@ -229,6 +229,43 @@ struct FfData : FfTypeData {
 	void flip_rst_bits(const pool<int> &bits);
 };
 
+struct FfDataSigMapped : public FfData {
+	SigMap& sigmap;
+	FfDataSigMapped(SigMap& map, Module *module, FfInitVals *initvals = nullptr, IdString name = IdString()) : FfData(module, initvals, name), sigmap(map) {}
+
+	void remap() {
+		sigmap(sig_q);
+		sigmap(sig_d);
+		sigmap(sig_ad);
+		sigmap(sig_clk);
+		sigmap(sig_ce);
+		sigmap(sig_aload);
+		sigmap(sig_arst);
+		sigmap(sig_srst);
+		sigmap(sig_clr);
+		sigmap(sig_set);
+	}
+	FfDataSigMapped(SigMap& map, FfInitVals *initvals, Cell *cell_) : FfData(initvals, cell_), sigmap(map) {
+		remap();
+	}
+	FfDataSigMapped(SigMap& map, const FfData& base) : FfData(base), sigmap(map) {
+		remap();
+	}
+	FfDataSigMapped(const FfDataSigMapped& other) : FfData(other), sigmap(other.sigmap) {}
+	FfDataSigMapped& operator=(const FfDataSigMapped& other) {
+		FfData::operator=(other);
+		return *this;
+	}
+	Cell* emit() {
+		Cell* cell = FfData::emit();
+		remap();
+		return cell;
+	}
+	FfDataSigMapped slice(const std::vector<int> &bits) {
+		return FfDataSigMapped(sigmap, FfData::slice(bits));
+	}
+};
+
 YOSYS_NAMESPACE_END
 
 #endif

kernel/ffmerge.cc

@@ -303,6 +303,7 @@ void FfMergeHelper::remove_output_ff(const pool<std::pair<Cell *, int>> &bits) {
 		dff_driver.erase((*sigmap)(q[idx]));
 		q[idx] = module->addWire(stringf("$ffmerge_disconnected$%d", autoidx++));
 		cell->setPort(ID::Q, q);
+		initvals->set_init(cell->getPort(ID::Q), (*initvals)(q));
 	}
 }
 

kernel/mem.cc

@@ -349,8 +349,11 @@ void Mem::emit() {
 			bool v2 = !init.en.is_fully_ones();
 			if (!init.cell)
 				init.cell = module->addCell(NEW_ID, v2 ? ID($meminit_v2) : ID($meminit));
-			else
+			else {
+				if (!v2)
+					init.cell->unsetPort(ID::EN);
 				init.cell->type = v2 ? ID($meminit_v2) : ID($meminit);
+			}
 			init.cell->attributes = init.attributes;
 			init.cell->parameters[ID::MEMID] = memid.str();
 			init.cell->parameters[ID::ABITS] = GetSize(init.addr);
@@ -361,8 +364,6 @@ void Mem::emit() {
 			init.cell->setPort(ID::DATA, init.data);
 			if (v2)
 				init.cell->setPort(ID::EN, init.en);
-			else
-				init.cell->unsetPort(ID::EN);
 		}
 	}
 }

kernel/rtlil.cc

@@ -1215,22 +1215,6 @@ RTLIL::Module *RTLIL::Design::top_module() const
 	return module_count == 1 ? module : nullptr;
 }
 
-void RTLIL::Design::add(RTLIL::Module *module)
-{
-	log_assert(modules_.count(module->name) == 0);
-	log_assert(refcount_modules_ == 0);
-	modules_[module->name] = module;
-	module->design = this;
-
-	for (auto mon : monitors)
-		mon->notify_module_add(module);
-
-	if (yosys_xtrace) {
-		log("#X# New Module: %s\n", log_id(module));
-		log_backtrace("-X- ", yosys_xtrace-1);
-	}
-}
-
 void RTLIL::Design::add(RTLIL::Binding *binding)
 {
 	log_assert(binding != nullptr);
@@ -1528,6 +1512,7 @@ RTLIL::Module::Module()
 
 RTLIL::Module::~Module()
 {
+	clear_sig_norm_index();
 	for (auto &pr : wires_)
 		delete pr.second;
 	for (auto &pr : memories)
@@ -2740,7 +2725,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 	new_mod->avail_parameters = avail_parameters;
 	new_mod->parameter_default_values = parameter_default_values;
 
-	for (auto &conn : connections_)
+	for (auto &conn : connections())
 		new_mod->connect(conn);
 
 	for (auto &attr : attributes)
@@ -2948,23 +2933,6 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 	}
 }
 
-void RTLIL::Module::remove(RTLIL::Cell *cell)
-{
-	while (!cell->connections_.empty())
-		cell->unsetPort(cell->connections_.begin()->first);
-
-	log_assert(cells_.count(cell->name) != 0);
-	log_assert(refcount_cells_ == 0);
-	cells_.erase(cell->name);
-	if (design && design->flagBufferedNormalized && buf_norm_cell_queue.count(cell)) {
-		cell->type.clear();
-		cell->name.clear();
-		pending_deleted_cells.insert(cell);
-	} else {
-		delete cell;
-	}
-}
-
 void RTLIL::Module::remove(RTLIL::Memory *memory)
 {
 	log_assert(memories.count(memory->name) != 0);
@@ -3108,29 +3076,6 @@ void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs
 	connect(RTLIL::SigSig(lhs, rhs));
 }
 
-void RTLIL::Module::new_connections(const std::vector<RTLIL::SigSig> &new_conn)
-{
-	for (auto mon : monitors)
-		mon->notify_connect(this, new_conn);
-
-	if (design)
-		for (auto mon : design->monitors)
-			mon->notify_connect(this, new_conn);
-
-	if (yosys_xtrace) {
-		log("#X# New connections vector in %s:\n", log_id(this));
-		for (auto &conn: new_conn)
-			log("#X#    %s = %s (%d bits)\n", log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
-		log_backtrace("-X- ", yosys_xtrace-1);
-	}
-
-	connections_ = new_conn;
-}
-
-const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() const
-{
-	return connections_;
-}
 
 void RTLIL::Module::fixup_ports()
 {

kernel/rtlil.h

@@ -122,10 +122,19 @@ namespace RTLIL
 	struct Binding;
 	struct IdString;
 	struct OwningIdString;
+	struct StaticIdString;
+	struct SigNormIndex;
 
 	typedef std::pair<SigSpec, SigSpec> SigSig;
+	struct PortBit;
 };
 
+// TODO clean up?
+extern int64_t signorm_ns;
+extern int signorm_count;
+extern int64_t signorm_restore_ns;
+extern int signorm_restore_count;
+
 struct RTLIL::IdString
 {
 	struct Storage {
@@ -1892,7 +1901,9 @@ struct RTLIL::Design
 	dict<std::string, std::string> scratchpad;
 
 	bool flagBufferedNormalized = false;
+	bool flagSigNormalized = false;
 	void bufNormalize(bool enable=true);
+	void sigNormalize(bool enable=true);
 
 	int refcount_modules_;
 	dict<RTLIL::IdString, RTLIL::Module*> modules_;
@@ -2053,6 +2064,10 @@ struct RTLIL::Design
 
 struct RTLIL::Module : public RTLIL::NamedObject
 {
+	friend struct RTLIL::SigNormIndex;
+	friend struct RTLIL::Cell;
+	friend struct RTLIL::Design;
+
 	Hasher::hash_t hashidx_;
 	[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
 
@@ -2110,6 +2125,19 @@ struct RTLIL::Module : public RTLIL::NamedObject
 	pool<RTLIL::Cell *> pending_deleted_cells;
 	dict<RTLIL::Wire *, pool<RTLIL::Cell *>> buf_norm_connect_index;
 	void bufNormalize();
+	void dump_sigmap();
+
+protected:
+	SigNormIndex *sig_norm_index = nullptr;
+	void clear_sig_norm_index();
+	int timestamp_ = 0;
+public:
+	void sigNormalize();
+
+	int timestamp() const { return timestamp_; }
+	int next_timestamp();
+	std::vector<Cell *> dirty_cells(int starting_from);
+	const pool<PortBit> &fanout(SigBit bit);
 
 	template<typename T> void rewrite_sigspecs(T &functor);
 	template<typename T> void rewrite_sigspecs2(T &functor);
@@ -2430,6 +2458,7 @@ struct RTLIL::Wire : public RTLIL::NamedObject
 protected:
 	// use module->addWire() and module->remove() to create or destroy wires
 	friend struct RTLIL::Module;
+	friend struct RTLIL::SigNormIndex;
 	Wire();
 	~Wire();
 
@@ -2627,6 +2656,33 @@ struct RTLIL::Process : public RTLIL::NamedObject
 	std::string to_rtlil_str() const;
 };
 
+struct RTLIL::PortBit
+{
+	RTLIL::Cell *cell;
+	RTLIL::IdString port;
+	int offset;
+	PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}
+
+	bool operator<(const PortBit &other) const {
+		if (cell != other.cell)
+			return cell < other.cell;
+		if (port != other.port)
+			return port < other.port;
+		return offset < other.offset;
+	}
+
+	bool operator==(const PortBit &other) const {
+		return cell == other.cell && port == other.port && offset == other.offset;
+	}
+
+	[[nodiscard]] Hasher hash_into(Hasher h) const {
+		h.eat(cell->name);
+		h.eat(port);
+		h.eat(offset);
+		return h;
+	}
+};
+
 
 inline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { }
 inline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
@@ -2691,6 +2747,7 @@ inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
 template<typename T>
 void RTLIL::Module::rewrite_sigspecs(T &functor)
 {
+	log_assert(sig_norm_index == nullptr);
 	for (auto &it : cells_)
 		it.second->rewrite_sigspecs(functor);
 	for (auto &it : processes)
@@ -2704,6 +2761,7 @@ void RTLIL::Module::rewrite_sigspecs(T &functor)
 template<typename T>
 void RTLIL::Module::rewrite_sigspecs2(T &functor)
 {
+	log_assert(sig_norm_index == nullptr);
 	for (auto &it : cells_)
 		it.second->rewrite_sigspecs2(functor);
 	for (auto &it : processes)