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YosysHQ / yosys Public

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signorm: directed RTLIL, incremental optimization#5804

Draft

widlarizer wants to merge 79 commits into

mainYosysHQ/yosys:mainfrom

emil/signormYosysHQ/yosys:emil/signormCopy head branch name to clipboard

Conversation Commits79 (79)Checks Files changed

Draft

signorm: directed RTLIL, incremental optimization#5804
widlarizer wants to merge 79 commits into
mainfrom
emil/signorm

Commits

Commits on May 5, 2026

WIP remove dead code

jix
authored and
widlarizer
committed
WIP half broken snapshot

jix
authored and
widlarizer
committed
mem: fix signorm cell type morph
widlarizer
committed
check: don't fail on $input_port
widlarizer
committed
tests: adjust to input_port and init behavior (sketchy)
widlarizer
committed
rtlil_bufnorm: fix cell deletion deferral bug
widlarizer
committed
bug2920: disable
widlarizer
committed
rtlil: fix zero width SigSpec crash in signorm setPort unsetPort
widlarizer
committed
tests: adjust to input_port and init behavior (sketchy)
widlarizer
committed
ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire
widlarizer
committed
wreduce: fixup initvals after setPort
widlarizer
committed
tests: adjust to input_port and init behavior (sketchy)
widlarizer
committed
tests: adjust to input_port and init behavior (sketchy)
widlarizer
committed
tests: adjust to input_port and init behavior (sketchy)
widlarizer
committed
synth_ice40: always read abc9 model to understand port direction
widlarizer
committed
opt_merge_inc: re add initvals deletion
widlarizer
committed
rtlil: forbid rewrite_sigspecs in signorm
widlarizer
committed
timinginfo: disable output wire check due to signorm
widlarizer
committed
opt_hier: disable signorm
widlarizer
committed
techmap: disable signorm
widlarizer
committed
techmap: disable signorm more
widlarizer
committed
rtlil: add dump_sigmap for hacky signorm debugging
widlarizer
committed
satgen: support $connect
widlarizer
committed
opt_expr: fix invert_map
widlarizer
committed
signorm: disable in passes that use swap_names
widlarizer
committed
signorm: skip const when fixing fanout
widlarizer
committed
flatten: skip $input_port cells in template module
widlarizer
committed
abstract: skip $input_port cells
widlarizer
committed
signorm: remove $input cells when leaving
widlarizer
committed
check: stitch info about $connect ports together for driver analysis
widlarizer
committed
aiger: ignore $input_port
widlarizer
committed
signorm: disable passes that use rewrite_sigspecs
widlarizer
committed
abstract: fix test signorm
widlarizer
committed
flatten: redo signormalization to work around fanout issue
widlarizer
committed
cxxrtl: ignore $input_port
widlarizer
committed
design: fix signorm commit connectivity to design
widlarizer
committed
tests: fix rtlil roundtrip test
widlarizer
committed
opt_dff: temporarily disable signorm due to muxtree traversal
widlarizer
committed
ff: add FfDataSigMapped
widlarizer
committed
opt_dff: sigma harder, FfDataSigMapped
widlarizer
committed
connect: remove input ports on conflict
widlarizer
committed
opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
widlarizer
committed
timinginfo: special-case $specify2 in signorm invariant
widlarizer
committed
ffmerge: initvals signorm compatibility fixup
widlarizer
committed
memory_bram: add -register
widlarizer
committed
memory: add -bram-register
widlarizer
committed
tests: use memory -bram-register in tests/bram
widlarizer
committed
techmap: call hierarchy on map files to determine port directions
widlarizer
committed
hierarchy: tolerance for apparent recursive instances in techmap files
widlarizer
committed
Revert "techmap: call hierarchy on map files to determine port directions"
widlarizer
committed
gowin: replace positional arguments in cells_sim.v with named
widlarizer
committed
rtlil_bufnorm: ignore timing info harder
widlarizer
committed
intel: register bram celltypes
widlarizer
committed
rtlil_bufnorm: more xlog
widlarizer
committed
rtlil: sigNormalize Module when added to Design in signorm mode
widlarizer
committed
rtlil: fix cloneInto in signorm
widlarizer
committed
equiv_make: don't copy $input_port
widlarizer
committed
design: properly switch signorm mode when restoring saved designs
widlarizer
committed
rtlil_bufnorm: more xlog
widlarizer
committed
equiv_miter: don't copy $input_port
widlarizer
committed
gowin: rebless LUT counts
widlarizer
committed
pmgen: hold sigmap pointer instead of owning it
widlarizer
committed
xilinx_dsp: signorm compatibility
widlarizer
committed
nexus: loosen tests
widlarizer
committed
ecp5: loosen tests
widlarizer
committed
flatten: disable signorm
widlarizer
committed
gowin: loosen tests
widlarizer
committed
intel_alm: loosen tests
widlarizer
committed
Revert "memory_bram: add -register"
widlarizer
committed
Revert "memory: add -bram-register"
widlarizer
committed
Revert "tests: use memory -bram-register in tests/bram"
widlarizer
committed
Revert "intel: register bram celltypes"
widlarizer
committed
memory_bram: create blackboxes
widlarizer
committed
check: fix memory bug in $connect
widlarizer
committed
rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction
widlarizer
committed

Commits on May 6, 2026

signorm: add timers
widlarizer
committed
opt_expr: replace invert_map with signorm traversal
widlarizer
committed
opt_merge: factor out hashing code across incremental and parallel
widlarizer
committed
opt_merge: newcelltypes
widlarizer
committed

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