Add PLL clock source to clock_dict

README.md

@@ -1,5 +1,5 @@
 ![pynq_logo](https://github.com/Xilinx/PYNQ/raw/master/logo.png)
-### version 0.1.7
+### version 0.1.8
 
 PYNQ-Metadata is an open-source project from Xilinx and is part of the PYNQ ecosystem. It's aims are to provide an abstract description of reconfigurable system designs. It is currently used internally within PYNQ to represent the hardware design currently configured in the Programmable Logic of Zynq-based devices. It is currently in pre-release.  
 
@@ -37,6 +37,7 @@ All python code for the ``PYNQ-Metadata`` package can be found in the `/pynqmeta
 
 
 ## Changelog
+* v0.1.8 : Add parsing of clock select
 * v0.1.7 : Relaxing constraint on address mapping due to issues with rfsoc4x2_base parsing. 
 * v0.1.6 : Python3.11 support added (Thanks @modularizer) 
 * v0.1.5 : Prevent parsing error when external AXI ports are present in the design. 

pynqmetadata/__init__.py

@@ -29,4 +29,4 @@
 from .models.clk_port import ClkPort
 from .models.rst_port import RstPort
 
-__version__ = "0.1.7"
+__version__ = "0.1.8"

pynqmetadata/models/proc_sys_core.py

@@ -65,6 +65,22 @@ def gpio(self) -> Dict[str, object]:
 
             return ret
 
+    def find_clock_select(self, clk_id) -> int:
+        """For a given clock id return the selected PLL clock"""
+        src_sel_name = self.clk_src_sel_param_name(clk_id)
+        if src_sel_name in self.parameters:
+            src_sel = self.parameters[src_sel_name].value
+            if src_sel is not None:
+                return src_sel
+            else:
+                raise ValueError(
+                    f"Clock select {src_sel} for PL clock {clk_id} has no value"
+                )
+        else:
+            raise ParameterNotFound(
+                f"Unable to find a clock select {src_sel} for PL clock {clk_id}"
+            )
+
     def clk_div_param_name(self, clk_id: int, div_id: int) -> str:
         """Returns the name of the clock div parameter for this PS.
         Default is the same format as Ultrascale."""

pynqmetadata/models/ultrascale_proc_sys_core.py

@@ -25,3 +25,9 @@ def clk_div_param_name(self, clk_id: int, div_id: int) -> str:
     def clk_enable_param_name(self, clk_id: int) -> str:
         """Returns the parameter for the clock enable for clock with id clk_id on this PS"""
         return f"PSU__FPGA_PL{clk_id}_ENABLE"
+
+    def clk_src_sel_param_name(self, clk_id: int):
+        """Returns the name of the PL clock select parameter for given clk_id."""
+        return f"PSU__CRL_APB__PL{clk_id}_REF_CTRL__SRCSEL"
+
+

pynqmetadata/models/zynq_proc_sys_core.py

@@ -29,3 +29,7 @@ def clk_div_param_name(self, clk_id: int, div_id: int) -> str:
     def clk_enable_param_name(self, clk_id: int) -> str:
         """Returns the parameter for the clock enable for clock with ID clk_id on this PS"""
         return f"PCW_FPGA_FCLK{clk_id}_ENABLE"
+
+    def clk_src_sel_param_name(self, clk_id: int):
+        """Returns the name of the PL clock select parameter for given clk_id."""
+        return f"PCW_FCLK{clk_id}_PERIPHERAL_CLKSRC"

pynqmetadata/version.txt

@@ -1 +1 @@
-0.1.7
+0.1.8

pynqmetadata/views/runtime/clock_dict_view.py

@@ -36,6 +36,7 @@ def clock_dict(self) -> Dict:
                     repr_dict[i]["enable"] = int(core.find_clock_enable(i))
                     for j in range(2):
                         repr_dict[i][f"divisor{j}"] = core.find_clock_divisor(i, j)
+                    repr_dict[i]["src_sel"] = core.find_clock_select(i)
 
         return repr_dict