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phys_addr is not parsed correctly for IP on the BD root without special characters

Status: Open.

#29 In Xilinx/PYNQ-Metadata;

· mariodruiz opened on Jun 30, 2025

underscore_attrs_are_private: Pydantic v2 behaviour change

Status: Open.

#26 In Xilinx/PYNQ-Metadata;

· jogomojo opened on Jun 27, 2025

Hierarchies are not detected for newer Vivado versions

Status: Open.

#21 In Xilinx/PYNQ-Metadata;

· mariodruiz opened on Jun 19, 2024

Installation hangs due to broken resizer download

Status: Open.

#20 In Xilinx/PYNQ-Metadata;

· nocnokneo opened on May 31, 2024

HwhFrontend doesn't add Registers for AXI_FULL ports

Status: Open.

#14 In Xilinx/PYNQ-Metadata;

· TRnhld opened on Nov 17, 2023

Ability to add external AXI ports to block design for use with existing RTL

enhancementNew feature or requestNew feature or request

Status: Open.

#13 In Xilinx/PYNQ-Metadata;

· JonathanKnoblauch opened on Nov 7, 2023