Extended support of Alveo boards by BSC

.gitmodules

@@ -6,4 +6,7 @@
 	url = https://github.com/PrincetonUniversity/openpiton-aws.git
 [submodule "piton/design/chipset/rv64_platform/bootrom/u-boot/uboot"]
 	path = piton/design/chipset/rv64_platform/bootrom/u-boot/uboot
-	url = git@github.com:u-boot/u-boot.git
+	url = https://github.com/u-boot/u-boot.git
+[submodule "piton/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst"]
+	path = piton/design/chipset/io_ctrl/xilinx/common/ip_cores/eth_cmac_syst
+	url = https://github.com/bsc-loca/100gb-ethernet

README.md

@@ -505,3 +505,109 @@ The command will tell print the afi and agfi of your image. You can track the sy
 
 8. After the synthesis is done - you can go load it in your F1 instance!
 
+#### Synthesizing OpenPiton for ALVEO boards
+
+This section contains a description of extensions to OpenPiton developed by Barcelona Supercomputing Center (Copyright 2026 - BSC):
+
+> *These BSC extensions are licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use these extensions except in compliance with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
+> https://solderpad.org/licenses/SHL-2.1/
+> Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.*
+
+
+The flow is very simillar to synthesizing image for any other FPGA OpenPiton supports:
+
+1. Clone OpenPiton repo (BSC version):
+  - from BSC GitLab: git clone https://gitlab.bsc.es/hwdesign/frameworks/meep_openpiton/-/tree/merge/openpiton-dev_upstr
+  - from public GitHub: git clone https://github.com/bsc-loca/openpiton-fpga/tree/openpiton-dev_upst
+
+2. cd into repo, run these bash commands:
+
+```
+    source piton/piton_settings.bash
+    source piton/ariane_setup.sh
+    (Follow instructions in the top of the README in case this is the first time you install OpenPiton in your machine.)
+```
+
+4. Run the synthesis:
+
+```
+    protosyn --board alveou280 --design system --core ariane --x_tiles 1 --y_tiles 1 --uart-dmw ddr --zeroer_off
+
+    Extra avaialble protosyn options:
+             --eth                     # adding CMAC based Ethernet unit
+             --ethport <num>           # optional board-level Ethernet port (default=0)
+
+             --hbm                     # define HBM as primary system memory
+             --multimc <num>           # implement design with multiple <num> connections to system memory (valid only for HBM)
+             --multimc_indices <coma separated list> # optional list of particular edge tiles for above `multimc` option
+
+             --bram-test hello_world.c # compiling and runniing VCS-based simulation before synthesis
+             --verdi-dbg  # creating Verdi compliant simulation database for above test (verdi run inside ./build dir (-sx is optional): verdi -ssf ./novas.fsdb)
+
+             # Options to define Multi-FPGA partioning borders:
+             --fr_x <num>  # Tile X coordinate from which FPGA partition starts in horizontal direction, by default it is 0 meaning no partitioning
+             --fr_y <num>  # Tile Y coordinate from which FPGA partition starts in vertical direction, by default it is 0 meaning no partitioning
+             --to_x <num>  # Tile X coordinate at which FPGA partition finishes in horizontal direction, by default it is (x_tiles-1) meaning no partitioning
+             --to_y <num>  # Tile Y coordinate at which FPGA partition finishes in vertical direction, by default it is (y_tiles-1) meaning no partitioning
+             # Options to define physical ports utilized for Multi-FPGA partioning borders (0 means connection through Ethernet switch, 1 means P2P connection): 
+             --frx_port <num>  # QSFP port (0/1) to be used for start X FPGA partitioning border, by default: 0.
+             --fry_port <num>  # QSFP port (0/1) to be used for start Y FPGA partitioning border, by default: 0.
+             --tox_port <num>  # QSFP port (0/1) to be used for finish X FPGA partitioning border, by default: 0.
+             --toy_port <num>  # QSFP port (0/1) to be used for finish Y FPGA partitioning border, by default: 0.
+
+             # Options to define Multi-FPGA partioning borders:
+             --fr_x <num>  # Tile X coordinate from which FPGA partition starts in horizontal direction, by default it is 0 meaning no partitioning
+             --fr_y <num>  # Tile Y coordinate from which FPGA partition starts in vertical direction, by default it is 0 meaning no partitioning
+             --to_x <num>  # Tile X coordinate at which FPGA partition finishes in horizontal direction, by default it is (x_tiles-1) meaning no partitioning
+             --to_y <num>  # Tile Y coordinate at which FPGA partition finishes in vertical direction, by default it is (y_tiles-1) meaning no partitioning
+             # Options to define physical ports utilized for Multi-FPGA partioning borders (0 means connection through Ethernet switch, 1 means P2P connection): 
+             --frx_port <num>  # QSFP port (0/1) to be used for start X FPGA partitioning border, by default: 0.
+             --fry_port <num>  # QSFP port (0/1) to be used for start Y FPGA partitioning border, by default: 0.
+             --tox_port <num>  # QSFP port (0/1) to be used for finish X FPGA partitioning border, by default: 0.
+             --toy_port <num>  # QSFP port (0/1) to be used for finish Y FPGA partitioning border, by default: 0.
+```
+
+This will create a Vivado design under $ROOT_DIR/build/...
+
+5. After the synthesis is complete (takes about 2-3 hours on fast PC), you can program the FPGA via JTAG
+
+6. Probably you would need to reboot to be able to use the new QDMA PCIe interface.
+
+7. Now you can download from the intranet the bbl containing the Linux kernel, a script to load it to the SDRAM and the bitstream itself in case you want to skip steps above.
+
+```
+    /home/fpga-runnerMEEP/lagarto_sdk_deploy/rv64gc/
+```
+
+In a separated bash window, open a client for the UART:
+
+```
+    picocom -b 115200 /dev/ttyUSB2
+```
+
+8. Clone FPGA tools repo: https://gitlab.bsc.es/hwdesign/fpga/integration-lab/fpga-tools.git
+
+Issue the next commands inside the downloaded repo:
+
+```
+    ./fpga/load-bitstream-onic.sh qdma <fpga_bistream_name>.bit
+	./boot_riscv/boot_acme.sh <osbi_buildroot>.bin
+```
+
+You should be able to see Linux booting on the other terminal.
+
+##### Multi-FPGA (EMiX) extension of OpenPiton by BSC
+
+1. Technology Description
+
+EMiX is a scalable multi-FPGA emulation framework for large multi-core RISC-V systems that no longer fit within a single FPGA. It partitions a monolithic tiled many-core RTL design at NoC boundaries and deploys the resulting components across several interconnected FPGAs. This facilitates pre-silicon validation of larger systems while preserving OS-level visibility and software-stack execution. The current prototype targets an OpenPiton-style tiled architecture and demonstrates multi-core configuration distributed across multiple AMD Alveo U55c FPGAs on BSC's Makinote cluster. It supports full-system execution, including Linux boot, and keeps access to UART, HBM memory, and Ethernet through the FPGA hosting the chipset. EMiX bridges the gap between closed industrial multi-FPGA prototyping platforms and accessible academic infrastructure, and is open-sourced under mentioned above Solderpad Hardware License.
+
+2. Dependencies
+
+EMiX relies on the OpenPiton research platform as the tiled many-core/NoC-based architectural substrate. It also uses AMD/Xilinx IP on Alveo U55C devices, including Aurora 64B/66B for low-latency QSFP point-to-point communication, the UltraScale+ Integrated 100G Ethernet Subsystem (CMAC) for scalable Ethernet connectivity, AXI4-Stream infrastructure for multiplexing, channel mapping and clock-domain crossing, and auxiliary IPs such as Binary Counter and Processor System Reset. These are governed by their respective GPL or Xilinx end-user license terms.
+
+3. Functioning
+
+EMiX cuts a tiled many-core RTL design along NoC edges and assigns groups of tiles to different FPGAs. Cross-FPGA NoC traffic is converted into a unified AXI-Stream transport and carried over two complementary links: Aurora-based QSFP-1 direct point-to-point channels for adjacent FPGAs, and CMAC-based 100 Gb Ethernet over QSFP-0 for scalable cross-cluster connectivity. NoC-Aurora and NoC-CMAC bridges translate packets between the emulated on-chip network and the physical FPGA links The framework supports different partitioning strategies, such as horizontal or vertical cuts, and can scale by changing the number of cores, tiles, and FPGAs.
+
+More details about EMiX are provided in a paper [EMiX: Emulating Beyond Single-FPGA Limits](https://arxiv.org/abs/2604.27012).