Extended support of Alveo boards by BSC#150

Open

alekrop wants to merge 2201 commits into

PrincetonUniversity:openpiton-devfrom

bsc-loca:openpiton-dev_upst

This pull request is big! We're only showing the most recent 250 commits

Commits on Aug 30, 2024

Merge branch 'openpiton-dev' into ft/DDR4_acc
Alex Kropotov
committed
Fix of rounding in UART divisor calculation, critical for low freq (20 MHz).
Alexander Kropotov
committed

Commits on Sep 12, 2024

Update accelerator_def.csv to default NO option
Joan Teruel Jurado
committed

Commits on Sep 16, 2024

Merge branch 'ft/CMS_acc' into 'production'
Alexander Kropotov
committed
Sync with production.
Alexander Kropotov
committed
`accelerator_def.csv`: update of memory type notion for PCIe/Eth/Aurora
Alexander Kropotov
committed

Commits on Sep 18, 2024

`meep_shell/accelerator_def.csv `: adding support of multiple AXI ports for DDR mem (2 inactive ports are present by default).
Alexander Kropotov
committed

Commits on Sep 19, 2024

Eth test app: extending HBM case to DDR option.
Alexander Kropotov
committed

Commits on Sep 23, 2024

100GbE: update of Xilinx bare-metal drivers to 2024.1
Alexander Kropotov
committed

Commits on Sep 25, 2024

#TestCICD Merge branch 'ft/DDR4_acc' into production_origCVA6
Alex Kropotov
committed

Commits on Sep 27, 2024

Merge branch 'production_origCVA6' into 'production'
Alexander Kropotov
committed
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alex Kropotov
committed

Commits on Sep 29, 2024

#TestCICD Using `git apply` for Ariane patching.
Alexander Kropotov
committed
#TestCICD Merge branch 'production_origCVA6' into 'production'
Alex Kropotov
committed
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alex Kropotov
committed

Commits on Sep 30, 2024

Merge branch 'merge/bsc_ariane_patch' into 'production'
Alexander Kropotov
committed

Commits on Oct 2, 2024

#TestCICD Board dependent parameter for SDRAM address width (DDR or HBM) in meep shell.
Alexander Kropotov
committed
Merge branch 'production_origCVA6' into merge/DRAM_addr
Alex Kropotov
committed

Commits on Oct 3, 2024

Merge branch 'merge/DRAM_addr' into 'production'
Alexander Kropotov
committed
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Jan 10, 2025

Removing non-submodule based 100GbE.
Alexander Kropotov
committed

Commits on Jan 13, 2025

#TestCICD Replacing just TCL file for 100GbE with a repo as submodule containing sw test application, 100GbE uB-based prototype design.
Alexander Kropotov
committed

Commits on Jan 17, 2025

Merge branch 'production_origCVA6' into 'production'
Alexander Kropotov
committed

Commits on Jan 20, 2025

Merge remote-tracking branch 'origin/production_origCVA6' into merge/openpiton-dev_upstr
Alex Kropotov
committed

Commits on Jan 21, 2025

Initial user interface in protosyn and multi-channel NOC->AXI-St bridge.
Alexander Kropotov
committed

Commits on Jan 29, 2025

#TestCICD Update of 100GbE IP: making single DMA master port configurable in meaning of AXI protocol and data width.
Alex Kropotov
committed
Merge branch 'production_origCVA6' into ft/upd100GbE
Alex Kropotov
committed

Commits on Jan 30, 2025

Merge branch 'ft/upd100GbE' into 'production'
Alexander Kropotov
committed

Commits on Jan 31, 2025

#TestCICD 100GbE: some updates of both sw apps: syst and proto.
Alexander Kropotov
committed

Commits on Feb 1, 2025

Merge branch 'production_origCVA6' into 'production'
Alexander Kropotov
committed

Commits on Feb 3, 2025

Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Feb 6, 2025

Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Feb 20, 2025

#TestCICD Extension of using embedded 100GbE with DRAM as DMA memory.
Alexander Kropotov
committed

Commits on Feb 22, 2025

#TestCICD After adding 322MHz 100GbE domain, update of placement constraints to meet 322MHz timing closure.
Alexander Kropotov
committed

Commits on Feb 23, 2025

Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Feb 24, 2025

Merge branch 'merge/openpiton-dev_upstr' into openpiton-dev_upst
Alex Kropotov
committed

Commits on Feb 25, 2025

Merge branch 'production_origCVA6' into 'production'
Alexander Kropotov
committed
Merge remote-tracking branch 'origin/production_origCVA6' into dev/multi-fpga
Alexander Kropotov
committed

Commits on Feb 27, 2025

#TestCICD Introduction of non-cached logical access to DRAM through `virtual` tag in `devices.xml` instead of physical access through ncmem `noc_axi4_bridge`.
Alexander Kropotov
committed

Commits on Feb 28, 2025

Commits on Mar 1, 2025

Merge branch 'production_origCVA6' into 'production'
Alexander Kropotov
committed

Commits on Mar 2, 2025

Merge branch 'merge/openpiton-dev_upstr' into openpiton-dev_upst
Alex Kropotov
committed

Commits on Mar 3, 2025

Merge branch 'production_origCVA6' into dev/multi-fpga
Alexander Kropotov
committed

Commits on Mar 5, 2025

#TestCICD Moving Ethernet specific constraints inside 100GbE submodule.
Alexander Kropotov
committed
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed
Merge remote-tracking branch 'origin/production_origCVA6' into dev/multi-fpga
Alexander Kropotov
committed

Commits on Mar 6, 2025

Merge branch 'merge/openpiton-dev_upstr' into openpiton-dev_upst
Alex Kropotov
committed
Merge branch 'production_origCVA6' into 'production'
Alexander Kropotov
committed

Commits on Mar 7, 2025

Adding separated wiring for NOC connection between tiles, tested on 2x2 mesh configuration.
Alexander Kropotov
committed

Commits on Mar 8, 2025

Adding credit2valrdy and valrdy2credit conversions in between tile NOC paths.
Alexander Kropotov
committed

Commits on Mar 11, 2025

Better separation of NOC channels in `valrdy` domain.
Alexander Kropotov
committed

Commits on Mar 12, 2025

Insertion of Xilinx AXI-Stream interconnect (single-channel CDC configuration) in-between of each NOC inter-tile connection.
Alexander Kropotov
committed

Commits on Mar 13, 2025

Applying inverse clock to CDC stage of Xilinx AXI-St interconnect for CDC test purposes.
Alexander Kropotov
committed

Commits on Mar 15, 2025

Enabling 3->1 and 1->3 cross-mux in Xilinx AXI-St interconnects and using them for combining 3 NOC channels for each of inter-tile connections.
Alexander Kropotov
committed

Commits on Mar 17, 2025

Update of arbitrage in `nocs_muxer` based on AXI-St `TLAST` signal.
Alexander Kropotov
committed

Commits on Mar 18, 2025

Number of muxed-demuxed NOC channels is extended to `3*PITON_NUM_TILES`, thus giving 12 channels per horizont and 12 channels per vertical on 2x2 tested configuration (2 instances of 12-channel mux…
Alexander Kropotov
committed

Commits on Mar 20, 2025

Adding generation of true `TLAST` signal for AXI-stream in `valrdy` domain of NOC connections, tested on 2x2 configuration.
Alexander Kropotov
committed

Commits on Mar 21, 2025

Adding width conversion 64->256->256->64.
Alexander Kropotov
committed

Commits on Mar 22, 2025

Width conversion is changed to un-aligned value 248 instead of 256 in order to have free one byte for TDEST transmission.
Alexander Kropotov
committed

Commits on Mar 30, 2025

Moving both mux/demix to single `nocs_aurora_bridge`.
Alexander Kropotov
committed
Adding concat/deconcat of 8-bit TDEST with 248-bit TDATA to form full 256-bit TDATA intended for streaming Aurora.
Alexander Kropotov
committed

Commits on Mar 31, 2025

Adding independent clock for Aurora domain, and input/output FIFOs at NOC domain to exclude stalls inside NOC packets at in/out.
Alexander Kropotov
committed

Commits on Apr 1, 2025

Manual config of Inputs FIFOs is removed; output reset is added, but not used yet.
Alexander Kropotov
committed
A delayed by 16 clocks version of reset is applied to the `tile`.
Alexander Kropotov
committed

Commits on Apr 2, 2025

Increased delay to 64 clocks for reset applied to tiles; at top level Eth-related QSFP pins are temporarly commented out.
Alexander Kropotov
committed

Commits on Apr 3, 2025

Commits on Apr 4, 2025

Refactoring in `nocs_aurora_bridge` schematic.
Alexander Kropotov
committed
Making internal `noc` reset dependent on full status of Aurora.
Alexander Kropotov
committed

Commits on Apr 6, 2025

Some extended commented code.
Alexander Kropotov
committed
`TRDY` signal between `aur_fifo` and `rx_fifo` is tied to ResetN to imitate real Aurora which doesn't provide `TRDY` back-pressure in Rx channel. Accordingly `rx_fifo` depth is increased to max ava…
Alexander Kropotov
committed

Commits on Apr 7, 2025

Moving the AXI-stream datapath to Aurora (looback so far), the Aurora datapath requires flipping of TDATA/TKEEP buses.
Alexander Kropotov
committed

Commits on Apr 11, 2025

Extra intermediate fifos are removed; Tx 2->1 and Rx 1->2 AXIS interconnects are added to implement Rx side FIFO state transmission in order to suspend the Aurora traffic (Aurora doesn't have TREAD…
Alexander Kropotov
committed

Commits on Apr 13, 2025

Moving to Vivado-2024.2 because of correct config of inserted axis_injector, upgrade of Aurora to v.13. Tested on 2x2Ariane since Vivado-2024.2 fails to synthesize Lag-hun.
Alexander Kropotov
committed

Commits on Apr 15, 2025

Commits on Apr 16, 2025

Removing in "suspend_injector" passing of any `tdata`, just only `tdest` field. Tested on 2x2 configuration.
Alexander Kropotov
committed
Isolating `suspend_injector` from `suspend_flop` logic with extra FIFO in order to overcome AXI-stream interconnect auto-config issues.
Alexander Kropotov
committed
Changing thr priority of `suspend_injector` arbitrage to `fixed`.
Alexander Kropotov
committed

Commits on Apr 17, 2025

Commits on Apr 18, 2025

The size of `rx_fifo` is intentionally reduced to small value in order to check the functionality of introduced flow control.
Alexander Kropotov
committed

Commits on Apr 20, 2025

Rx overflow condition is reported to UART, light refactoring, core freq is returned to 100MHz.
Alexander Kropotov
committed
Applying distributed reset to Aurora according to spec.
Alexander Kropotov
committed

Commits on Apr 21, 2025

Using Reset generator for Aurora clock (`txrx`) domain.
Alexander Kropotov
committed

Commits on Apr 22, 2025

Removing extra reset inverter in Aurora domain.
Alexander Kropotov
committed

Commits on Apr 23, 2025

Number of channels is extended by one, meaning that channel#0 is devoted for trasmitting static signals like interrupts.
Alexander Kropotov
committed

Commits on Apr 25, 2025

#TestCICD Update of 100GbE IP: custom smart eth_rx_fifo is used instead of standard one from Xilinx.
Alexander Kropotov
committed

Commits on Apr 26, 2025

#TestCICD Update of 100GbE: increase of Rx FIFO depth.
Alexander Kropotov
committed

Commits on May 4, 2025

Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed
Merge branch 'production_origCVA6' into 'production'
Alexander Kropotov
committed

Commits on May 5, 2025

Merge remote-tracking branch 'origin/merge/openpiton-dev_upstr' into openpiton-dev_upst
Alex Kropotov
committed

Commits on May 6, 2025

Merge remote-tracking branch 'origin/production_origCVA6' into dev/multi-fpga
Alexander Kropotov
committed

Commits on May 13, 2025

Adding a patch for Lagarto to overcome Vivado-2024.2 synthesizer crash.
Alexander Kropotov
committed

Commits on May 14, 2025

Returning back Ethernet over QSFP-1 ports at top level. So for now Eth should be fixed to QSFP-1 and Aurora to QSFP-0.
Alexander Kropotov
committed

Commits on Jun 6, 2025

Conveying interrupts through chan#0 of Aurora bridge.
Alexander Kropotov
committed

Commits on Jun 9, 2025

Exchange of QSFP ports betwenn Aurora and 100GbE. Now 100GbE uses QSFP-0 and Aurora uses QSFP-1.
Alexander Kropotov
committed

Commits on Jun 12, 2025

Added power-up 128-clock length reset for Aurora.
Alexander Kropotov
committed

Commits on Jun 13, 2025

Length of powerup reset is increased: 20-bit counter.
Alexander Kropotov
committed

Commits on Jun 19, 2025

initial propagation of user options `--fr_x/y` and `--to_x/y` to configuration of RTL/nocs_aurora_bridge.
Alexander Kropotov
committed
Reset from `nocs_aur_bridge` is applied to tiles and occupied logic.
Alexander Kropotov
committed

Commits on Jun 20, 2025

Not instantating unneeded tiles in particular FPGA of multi-FPGAs.
Alexander Kropotov
committed

Commits on Jun 21, 2025

Elimination of initial noc muxer/demuxer.
Alexander Kropotov
committed

Commits on Jun 26, 2025

Elimination of extra `valrdy_to_credit` and `credit_to_valrdy` converters not participating in FPGA partitioning.
Alexander Kropotov
committed
Moving in SV Python `valrdy_last_gen` instances to the same loop with tiles' generation.
Alexander Kropotov
committed

Commits on Jun 27, 2025

Refactoring/optimising muti-fpga environment in `chip.sv.pyv`
Alexander Kropotov
committed

Commits on Jun 28, 2025

Bettre parameterisation and some refactoring of `axistx_aurora_bridge`.
Alexander Kropotov
committed

Commits on Jul 1, 2025

Optimization of `axis_muxer` and `axis_demuxer`.
Alexander Kropotov
committed

Commits on Jul 4, 2025

Moving AXI `tdest` signals from `chip.sv.pyv` to `axistx_aurora_bridge.tcl` since they don't need to be flexible but fixed to a port number.
Alexander Kropotov
committed

Commits on Jul 6, 2025

Increase FIFO depth of in/out and tx/rx FIFOs.
Alexander Kropotov
committed

Commits on Jul 10, 2025

Refactor to support compatibility with regular single-FPGA flow.
Alexander Kropotov
committed

Commits on Jul 12, 2025

#TestCICD Add mutually exclusive Aurora constraints for QSFP0/QSFP1.
Alexander Kropotov
committed
#TestCICD Do not create AXI-St-Aurora bridge by running TCL if multi-FPGA config is not present.
Alexander Kropotov
committed

Commits on Jul 13, 2025

Merge branch 'production_origCVA6' into production
Alexander Kropotov
committed
Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Jul 14, 2025

Fix: eliminate SystemVerilog syntax from `chip.v.pyv`.
Alexander Kropotov
committed
#TestCICD Fix: eliminate SystemVerilog syntax from chip.sv.pyv to be complient with original OP chip.v.pyv.
Alexander Kropotov
committed
#TestCICD Merge branch 'production_origCVA6' into production: eliminate SystemVerilog syntax from chip.sv.pyv to be complient with original OP chip.v.pyv.
Alexander Kropotov
committed

Commits on Jul 18, 2025

#TestCICD Fix: the constant connected to READY of FlowControl Rx FIFO was occasionally set to zero.
Alexander Kropotov
committed
#TestCICD Merge branch 'production_origCVA6' into production
Alexander Kropotov
committed

Commits on Jul 21, 2025

Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Aug 3, 2025

Initial commit of dual-fpga through P2P CMAC (100GbE).
Alexander Kropotov
committed
Multi-fpga: restore of application of reset to tiles taken from `noc_cmac_bridge`.
Alexander Kropotov
committed

Commits on Aug 4, 2025

multi-fpga based on P2P CMAC: making secondary resets dependent on CMAC full rx/tx state.
Alexander Kropotov
committed

Commits on Aug 8, 2025

Added bring-up procedure according to the spec through driving `ctl_tx_send_rfi` by syncronized `stat_rx_aligned`.
Alexander Kropotov
committed

Commits on Aug 9, 2025

Multi-fpga: refactor of resets in `axistx_cmac_bridge`
Alexander Kropotov
committed

Commits on Sep 1, 2025

Partial unification of CMAC and Auroara based multi-fpga solution.
Alexander Kropotov
committed

Commits on Sep 3, 2025

#TestCICD Adding separate XDC constraints for CMAC based multi-fpga solution.
Alexander Kropotov
committed

Commits on Sep 5, 2025

#TestCICD Merge branch 'production_origCVA6' into production
Alexander Kropotov
committed

Commits on Sep 9, 2025

Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Sep 10, 2025

Initial commit with Ethernet frame header support, not so far used for `NOC-CMAC` bridge case.
Alexander Kropotov
committed

Commits on Sep 11, 2025

Fix of connections for `NOC-CMAC` bridge with added Eth header. It is built succesfuly but functionality doesn't work so far. With `NOC-Aurora` bridge dual-fpga functionality is saved (should work).
Alexander Kropotov
committed

Commits on Sep 12, 2025

Commits on Sep 13, 2025

True enable of addition/remove of Eth frame header before/after `NOC-CMAC` bridge.
Alexander Kropotov
committed

Commits on Sep 16, 2025

Added Eth header to the packet with interrupts.
Alexander Kropotov
committed
Fixing typo.
Alexander Kropotov
committed

Commits on Sep 18, 2025

Added write/read from/to PCIe dest/source MAC address for Eth header in multi-FPGA.
Alexander Kropotov
committed

Commits on Sep 21, 2025

Applying hex debug texts for reading dummy Rx Eth packet fields (Auro-based multi-FPGA partitioning or partitioning absence).
Alexander Kropotov
committed

Commits on Sep 24, 2025

Addding readback of normal control from PCIe GPIO.
Alexander Kropotov
committed

Commits on Sep 25, 2025

Output of Eth header to PCIe GPIO is changed to normal NOC channels instead of previous interrupts' one.
Alexander Kropotov
committed

Commits on Sep 26, 2025

Merge branch 'production_origCVA6' into merge/openpiton-dev_upstr
Alexander Kropotov
committed
Fix typo.
Alexander Kropotov
committed

Commits on Oct 1, 2025

Merge branch 'production_origCVA6' into 'production'
Alexander Kropotov
committed

Commits on Oct 20, 2025

Update of 100GbE IP.
Alexander Kropotov
committed

Commits on Oct 22, 2025

Multi-FPGA: always resetting `noc-qsfp` bridge by main reset (from PCIe) and getting reset for tiles from `noc-qsfp` bridge on both sides
Alexander Kropotov
committed

Commits on Oct 25, 2025

NOC-Eth bridging: Added check of correctness of recieved Eth frame header, if not correct the packet is ignored.
Alexander Kropotov
committed

Commits on Oct 27, 2025

Added ILA to AXIS Rx channels.
Alexander Kropotov
committed

Commits on Oct 28, 2025

Swap of bytes in payload length of Eth frame header for Big-end network byte order.
Alexander Kropotov
committed

Commits on Oct 29, 2025

Eth-based multi-fpga: FC (flow control) schematic is skipped, thus doesn't function anymore.
Alexander Kropotov
committed

Commits on Oct 30, 2025

Replacing in Ethertype field of Eth frame header true Eth payload lenght (old notation) with custom Ethertype value not utilized in IEEE 802.
Alexander Kropotov
committed

Commits on Oct 31, 2025

Doubling number of channels in nocs-eth bridge for confirmation transmission, with according extension of interfaces of `valrdy_to_ethframe` and `ethframe_to_valrdy` modules, so far not utilized yet.
Alexander Kropotov
committed

Commits on Nov 3, 2025

Adding unique Eth frame ID to Eth header to be further checked on Rx side and back retransmitted as reception confirmation.
Alexander Kropotov
committed

Commits on Nov 4, 2025

Back transmission of confirmation of correctly recieved packet is added.
Alexander Kropotov
committed

Commits on Nov 6, 2025

Added but not enabled wait and reception of acknoledgement of transferred NOC Eth packet on Tx side.
Alexander Kropotov
committed
For debug relaxing the check of recieved ACK packet on Tx side: only DST/SRC MAC addr and Eth type, without Eth frame ID.
Alexander Kropotov
committed
Adding Eth frame ID to the ACK header check on Tx side.
Alexander Kropotov
committed

Commits on Nov 7, 2025

Added retry transmission if no packet ACK recieved.
Alexander Kropotov
committed

Commits on Nov 10, 2025

Added report of ACK wait time and number of retries.
Alexander Kropotov
committed

Commits on Nov 14, 2025

Commits on Nov 17, 2025

Some refactoring of CMAC Eth packet filtering, other clean-ups.
Alexander Kropotov
committed

Commits on Nov 18, 2025

Making as default not registered inputs in `ethcmac_to_demux.sv` Eth filter/fifo coming from CMAC.
Alexander Kropotov
committed

Commits on Nov 19, 2025

Sync-up new production with `production_origCVA6`
Alexander Kropotov
committed
Merge remote-tracking branch 'origin/production' into dev/multi-fpga-eth
Alexander Kropotov
committed
Eth header: IEEE802.3 usage of Ethertype field as Eth payload length.
Alexander Kropotov
committed

Commits on Nov 20, 2025

Update of format of GPIO line for Wrapper FPGA Shell.
Alexander Kropotov
committed

Commits on Nov 21, 2025

Update of notation for UART for implementation under FPGA(MEEP)_Shell, now assuming few UART ports.
Alexander Kropotov
committed

Commits on Nov 26, 2025

Merge branch 'production' into dev/multi-fpga-eth
Alexander Kropotov
committed
Some cleanup of `axistx_cmac_bridge.tcl`.
Alexander Kropotov
committed

Commits on Nov 28, 2025

Added muxer/demuxer cascading in `axistx_cmac_bridge`
Alexander Kropotov
committed

Commits on Nov 29, 2025

Commits on Dec 2, 2025

Light reformatting.
Alexander Kropotov
committed
Merge branch 'acme_v80' into 'production'
Alexander Kropotov
committed
Merge remote-tracking branch 'origin/production' into dev/multi-fpga-eth
Alexander Kropotov
committed

Commits on Dec 3, 2025

Merge branch 'production' into merge/openpiton-dev_upstr
Alexander Kropotov
committed
Syntax fix for Verilog-2005.
Alexander Kropotov
committed

Commits on Dec 4, 2025

Updated wait-ack timeout, other cleanups.
Alexander Kropotov
committed
Merge branch 'production' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Dec 7, 2025

Initial refactoring for moving to indendant usage of Aurora and/or CMAC based `NOC-QSFP` bridges.
Alexander Kropotov
committed

Commits on Dec 8, 2025

Fix of partitioning through Aurora when only one limit (to_ or fr_) is is involved, the case of real partitoning between 2 FPGAs.
Alexander Kropotov
committed

Commits on Dec 10, 2025

Commits on Dec 11, 2025

Refactoring of interrupt transmission, for Aurora/CMAC simultenious usage.
Alexander Kropotov
committed

Commits on Dec 12, 2025

Fix of AXISt interconnect cascading with evenly distributed channels per muxer/demuxer.
Alexander Kropotov
committed

Commits on Dec 15, 2025

Extra reset of CMAC by Aurora since such reset may come from adjacent FPGA throgh P2P QSFP; Fix of partition case when it takes horz or vert size of a single tile.
Alexander Kropotov
committed

Commits on Dec 17, 2025

Excluding extra reset to CMAC from Aurora. Refactoring of generation of channels in both instances of Aurora and CMAC.
Alexander Kropotov
committed

Commits on Dec 18, 2025

Extension of AXISt-Aurora bridge upto 128 channels by cascading Xilinx AXI-St interconnect.
Alexander Kropotov
committed

Commits on Jan 6, 2026

Specialization of Dest MAC address for "FROM" and "TO" borders.
Alexander Kropotov
committed

Commits on Jan 9, 2026

Fix: extra specialization of "near" wires for proper separation of "FROM" and "TO" borders when both designate the same coordinate and both utilize CMAC Ethernet.
Alexander Kropotov
committed

Commits on Jan 14, 2026

Eth CMAC: Dedication of even ports to "FROM" border and odd ports to "TO" border.
Alexander Kropotov
committed

Commits on Jan 21, 2026

Support of different data widths over multiple channels for the both QSFP bridges, intended for transmitting signals like interrupts.
Alexander Kropotov
committed

Commits on Jan 22, 2026

Light parameter refactoring.
Alexander Kropotov
committed

Commits on Jan 26, 2026

Refactoring to locate "TO" channels above all "FROM" channels, thus giving single offset to their DEST address equal to doubled horz or vert number of tiles.
Alexander Kropotov
committed

Commits on Jan 27, 2026

Fix moving the loop over NOCs inside "FROM/TO" branches, accordingly with correction of required channel offset.
Alexander Kropotov
committed
Making Eth ACK channel width equal to CMAC used word (448 bits) in order to exclude width converters in half of channels.
Alexander Kropotov
committed

Commits on Jan 29, 2026

Fix: Roll-back to widths of "ACK" channel as NOC width + adding TKEEP (Byte enable) AXI-St signals to the channels of both bridges to designate clearly for Xilinx interconnects the valid bytes.
Alexander Kropotov
committed

Commits on Jan 30, 2026

Commits on Feb 2, 2026

Fix: more acurate calculation of number of evenly distributed channels per cascade part of muxer/demuxer.
Alexander Kropotov
committed

Commits on Feb 4, 2026

Applying to incoming to Eth ACK channel width equal to CMAC used word (448 bits), with explicit width of muxer xbar to be NOC 64 bits width for feasible implementation.
Alexander Kropotov
committed

Commits on Feb 5, 2026

Setting input to noc-Eth bridge width of ACK channels as NOC width (64 bits) since anyway the width of input Xbar is set to NOC width to avoid its routing congestion.
Alexander Kropotov
committed
Upgrade to Vivado-2025.2
Alexander Kropotov
committed

Commits on Feb 7, 2026

Relaxing clock (using system one) on first-level muxer Xbar for routing feasibility in case of large number of channels to be partitioned, like for 8x8-core OP configuration.
Alexander Kropotov
committed

Commits on Feb 8, 2026

Multi-FPGA throgh Eth: increasing default depth of primary Rx FIFO accepting Eth packets.
Alexander Kropotov
committed

Commits on Feb 9, 2026

Extra registering of static MAC addresses got from PCIe for better inter-clock routing.
Alexander Kropotov
committed

Commits on Feb 16, 2026

Excluding output reset from CMAC from general Tile reset.
Alexander Kropotov
committed

Commits on Feb 17, 2026

CMAC Rx fault signals are removed from contribution to CMAC output reset.
Alexander Kropotov
committed
Decoupling Tile reset from both Aurora and CMAC secondary resets.
Alexander Kropotov
committed

Commits on Feb 18, 2026

Returning dependency of Tile reset on both Aurora and CMAC, applying Aurora out reset to CMAC reset.
Alexander Kropotov
committed

Commits on Feb 19, 2026

Aurora output reset is not applied to CMAC.
Alexander Kropotov
committed

Commits on Feb 26, 2026

Some clean-up of resets usage: a bit simpler generation them from CMAC/Aurora states, and applying resets to readyness of data consumers around CMAC/AUrora bridegs (to compensate their probable dif…
Alexander Kropotov
committed

Commits on Feb 27, 2026

Fix: returning back `stat_rx_aligned` signal from CMAC to reset contribution.
Alexander Kropotov
committed
Returned back `TX_INIT` state from CMAC to reset contribution.
Alexander Kropotov
committed

Commits on Feb 28, 2026

Masking by reset signals valid/ready between Aurora master AXI-St and `valrdy_to_credit` unit to exclude interactions for earlier release of Aurora reset.
Alexander Kropotov
committed

Commits on Mar 1, 2026

Added 256-clock delay to Tile reset after Aurora/CMAC are brought-up.
Alexander Kropotov
committed

Commits on Mar 2, 2026

Extra reset of CMAC by Aurora since such reset may come from adjacent FPGA throgh P2P QSFP
Alexander Kropotov
committed

Commits on Mar 3, 2026

Additionally delayed reset (after Tile reset) to standby packets from NOC-Aurora bridge in order to ramp-up the Tile.
Alexander Kropotov
committed

Commits on Mar 5, 2026

Guard reset is extended 13th bit of counter.
Alexander Kropotov
committed
Removing Auraora out reset contribution to CMAC in reset.
Alexander Kropotov
committed

Commits on Mar 6, 2026

Increasing the duration of `guard` reset.
Alexander Kropotov
committed

Commits on Mar 7, 2026

Commits on Mar 8, 2026

Inrease of Tx fifo in Aurora bridge.
Alexander Kropotov
committed

Commits on Mar 12, 2026

Adding unconditional accept of Eth frames with extra buffering in `ethframe_to_valrdy` module since they are retransmitted infinitely until acknowledged and thus might fill-up the pipeline in the b…
Alexander Kropotov
committed

Commits on Mar 13, 2026

Alignment depth of Tx/Rx fifos in all bridges to 512.
Alexander Kropotov
committed

Commits on Mar 16, 2026

The length of guard tile reset is reduced to 4096 cycles. Tile reset now is applied without extra delay.
Alexander Kropotov
committed

Commits on Mar 17, 2026

Light refactoring of guard reset, now applyed to `valrdy_to_credit` module instead of previously `ethframe_to_valrdy`, what is more reliable not to start accepting eth frame in its middle after `rs…
Alexander Kropotov
committed

Commits on Mar 18, 2026

Fix: `valrdy_to_credit` should be reset earlier to be able to accept immediately `valid` signal from Aurora bridge after `rstn_guard` is released.
Alexander Kropotov
committed

Commits on Mar 19, 2026

Merge branch 'production' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Mar 24, 2026

Out fifo size is increased to 64.
Alexander Kropotov
committed

Commits on Apr 3, 2026

Merge branch 'production' into merge/openpiton-dev_upstr
Alexander Kropotov
committed

Commits on Apr 29, 2026

Merge branch 'merge/openpiton-dev_upstr' into openpiton-dev_upst
Alexander Kropotov
committed

Commits on May 4, 2026

Readme is extended with Multi-FPGA implementation options.
Alexander Kropotov
committed
Readme is extended with Multi-FPGA implementation options.
Alexander Kropotov
committed
Merge branch 'merge/openpiton-dev_upstr' into openpiton-dev_upst
Alexander Kropotov
committed

Commits on May 13, 2026

Adding description of Multi-FPGA extension to README.
Alexander Kropotov
committed
Typos in Readme.
Alexander Kropotov
committed
More typos in Readme.
Alexander Kropotov
committed
Merge branch 'production' into merge/openpiton-dev_upstr
Alexander Kropotov
committed
Merge branch 'merge/openpiton-dev_upstr' into openpiton-dev_upst
Alexander Kropotov
committed