Verilog_RTL

A comprehensive series of RTL design tutorials covering various aspects of digital design

Name		Name	Last commit message	Last commit date
001-004 Verilog Primer-Modelling Styles		001-004 Verilog Primer-Modelling Styles
005 Heirarchial Design		005 Heirarchial Design
006-008 HALF ADDER		006-008 HALF ADDER
009-011 FULL ADDER		009-011 FULL ADDER
012 FA_BY_HA		012 FA_BY_HA
013 RCA		013 RCA
014 8bit RCA		014 8bit RCA
015 n bit RCA		015 n bit RCA
016 Multi Adders		016 Multi Adders
017 4bit CLA		017 4bit CLA
018 8bit CLA		018 8bit CLA
019 HALF SUBTRACTOR		019 HALF SUBTRACTOR
020 FULL SUBTRACTOR		020 FULL SUBTRACTOR
021 FS_BY_HS		021 FS_BY_HS
022 ADDER CUM SUBTRACTOR		022 ADDER CUM SUBTRACTOR
023 ADDER SUBTRACTOR 4 BIT		023 ADDER SUBTRACTOR 4 BIT
024 ADDER SUBTRACTOR N BIT		024 ADDER SUBTRACTOR N BIT
025 OVERFLOW		025 OVERFLOW
026 MAG_COMPARATOR		026 MAG_COMPARATOR
027 N_BIT_MAG_COMPARATOR		027 N_BIT_MAG_COMPARATOR
028 MULTIPLIER 2 BIT		028 MULTIPLIER 2 BIT
029 BINARY TO GRAY CODE CONVERTOR		029 BINARY TO GRAY CODE CONVERTOR
030 GRAY TO BINARY CODE CONVERTOR		030 GRAY TO BINARY CODE CONVERTOR
031 BINARY TO EXCESS3 CODE CONVERTOR		031 BINARY TO EXCESS3 CODE CONVERTOR
032 BINARY TO BCD		032 BINARY TO BCD
033 BCD TO BINARY		033 BCD TO BINARY
034 2x1 MUX		034 2x1 MUX
035 4x1 MUX		035 4x1 MUX
036 4x1 MUX Using 2x1 MUx		036 4x1 MUX Using 2x1 MUx
037 8x1 MUX_by_2x1,4x1		037 8x1 MUX_by_2x1,4x1
038 Nx1 Mux		038 Nx1 Mux
039 Mux_2x1 N bit		039 Mux_2x1 N bit
040 1x2 DEMUX		040 1x2 DEMUX
041 1x4 DEMUX		041 1x4 DEMUX
042 1x16 USING 1X4 DEMUX		042 1x16 USING 1X4 DEMUX
043 1x2 DECODER		043 1x2 DECODER
044 2x4 DECODER		044 2x4 DECODER
045 3x8 BY 1x2_2x4 DECODER		045 3x8 BY 1x2_2x4 DECODER
046 4x16 BY 2x4 DECODER		046 4x16 BY 2x4 DECODER
047 NxM Decoder		047 NxM Decoder
048 2x1 ENCODER		048 2x1 ENCODER
049 4x2 ENCODER		049 4x2 ENCODER
050 8x3 ENCODER		050 8x3 ENCODER
051 NxM ENCODER		051 NxM ENCODER
052 PRIORITY ENCODER		052 PRIORITY ENCODER
053 NBit PRIORITY ENCODER		053 NBit PRIORITY ENCODER
054 Gated SR Latch		054 Gated SR Latch
055 Gated D Latch		055 Gated D Latch
056 D Latch		056 D Latch
057 D Latch By 2x1 Mux		057 D Latch By 2x1 Mux
058 D FF By D Latch		058 D FF By D Latch
059 D FF By 2x1 Mux		059 D FF By 2x1 Mux
060 COMPARE STORAGE ELEMENTS		060 COMPARE STORAGE ELEMENTS
061 SR FLIP FLOP		061 SR FLIP FLOP
062 JK FLIP FLOP		062 JK FLIP FLOP
063 T FLIP FLOP		063 T FLIP FLOP
064 D FLIPFLOP		064 D FLIPFLOP
065-067 SR TO JK,T,D		065-067 SR TO JK,T,D
068-070 JK TO SR,T,D		068-070 JK TO SR,T,D
071-073 T TO SR,JK,D		071-073 T TO SR,JK,D
074-076 D TO SR,JK,T		074-076 D TO SR,JK,T
077 ASYNCHRONOUS RESET		077 ASYNCHRONOUS RESET
078 SYNCHRONOUS RESET		078 SYNCHRONOUS RESET
079 BLOCKING & NON BLOCKING		079 BLOCKING & NON BLOCKING
080 Simple Register		080 Simple Register
081 Simple Register with Load		081 Simple Register with Load
082-085 Shift Registers Structural		082-085 Shift Registers Structural
086-089 Shift Registers Behavioral		086-089 Shift Registers Behavioral
090-092 UP Conters		090-092 UP Conters
093-095 Down Counter		093-095 Down Counter
096-098 Mod counters		096-098 Mod counters
099 Ring Counter		099 Ring Counter
100 Johnson Counter		100 Johnson Counter
LICENSE		LICENSE
README.md		README.md

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