feat(rockchip-rga): add the RK3588 RGA2 2D accelerator driver with /dev/rga and dma-heap

drivers/ax-driver/Cargo.toml

@@ -68,7 +68,7 @@ serial = [
     "dep:some-serial",
 ]
 rknpu = ["rockchip-pm", "rockchip-soc", "dep:rockchip-npu"]
-rga = ["dep:rockchip-rga"]
+rga = ["rockchip-pm", "rockchip-soc", "dep:rockchip-rga"]
 jpeg = ["rockchip-pm", "rockchip-soc", "dep:rockchip-jpeg"]
 jpu-selftest = ["jpeg"]
 rockchip-sdhci = [

drivers/ax-driver/src/rga.rs

@@ -1,18 +1,22 @@
 use alloc::vec::Vec;
 
-use log::info;
+use log::{info, warn};
 use rdrive::{
     probe::OnProbeError,
     register::{FdtInfo, ProbeFdt},
 };
-use rockchip_rga::{RgaCoreConfig, RgaCoreResource, RockchipRga};
+use rockchip_pm::{PowerDomain, RockchipPM};
+use rockchip_rga::{RgaCoreConfig, RgaCoreResource, RgaVersion, RockchipRga};
 
 use crate::mmio::iomap;
 
 crate::model_register!(
     name: "Rockchip RGA",
     level: ProbeLevel::PostKernel,
     priority: ProbePriority::DEFAULT,
+    // Match all three RGA cores. rdrive probes each matching FDT node independently (its probed
+    // set is keyed per node, not per driver), so every core gets its own probe() call; PR-1
+    // brings up RGA2 and defers the RGA3 cores in probe().
     probe_kinds: &[
         ProbeKind::Fdt {
             compatibles: &[
@@ -30,30 +34,119 @@ fn probe(probe: ProbeFdt<'_>) -> Result<(), OnProbeError> {
     let config = detect_core_config(&info)
         .ok_or_else(|| OnProbeError::other("unsupported Rockchip RGA compatible string"))?;
 
+    // PR-1 brings up RGA2 only. RGA3's clock tree / reset / real version-register offset are
+    // unverified and deferred to a later phase, so skip the RGA3 cores here (they still each get a
+    // probe() call now that rdrive probes every matching node). Skipping before any MMIO avoids
+    // the synchronous external abort an unclocked/unverified RGA3 version-read would raise.
+    if config.version == RgaVersion::Rga3 {
+        info!(
+            "RGA3 core (index {}) probe deferred in PR-1; skipping (RGA2-only bring-up)",
+            config.core_index
+        );
+        return Ok(());
+    }
+
+    // Bring the RGA2 core onto the bus BEFORE any MMIO: RgaCore::new reads the version register
+    // at base+0x28, which raises a synchronous external abort if the bus-interface clocks are
+    // still gated (U-Boot leaves the RGA clocks off at handoff). Power the domain, then ungate
+    // aclk/hclk/clk. If the clocks cannot be established, skip the core rather than fault the
+    // kernel on the version read.
+    enable_power(config);
+    if let Err(e) = enable_rga2_clocks(&info) {
+        warn!("RGA2 clock bring-up failed ({e}); skipping core to avoid an MMIO abort");
+        return Ok(());
+    }
+    deassert_rga2_resets(&info);
+
+    let irq = crate::binding_info_from_fdt(&info)?.irq_num();
+
     let mut resources = Vec::new();
     for reg in info.node.regs() {
         let start_raw = reg.address as usize;
         let size_raw = reg.size.unwrap_or(0x1000) as usize;
         let (start, size, offset) = page_aligned_region(start_raw, size_raw);
+        // SAFETY: `start`/`size` are a page-aligned MMIO window from the FDT `reg`; iomap maps it and `offset` is within it.
         let base = unsafe { iomap(start, size)?.add(offset) };
-
         resources.push(RgaCoreResource {
             base,
             size: size_raw,
-            irq: decode_fdt_irq(&info.interrupts()),
+            irq,
             config,
         });
     }
 
     let dma = axklib::dma::device_with_mask(u32::MAX as u64);
     let rga = RockchipRga::new(&resources, dma);
     let core_count = rga.core_count();
+    let version = rga.cores().first().map(|c| c.version());
     plat_dev.register(rga);
+    info!("RGA registered: cores={core_count} version={version:?}");
+    Ok(())
+}
 
-    info!("RGA registered successfully, cores={core_count}");
+fn enable_power(config: RgaCoreConfig) {
+    // RK3588 power-domain IDs (from rockchip-pm rk3588 variant): RGA30=22, RGA31=30, RGA2/VDPU=21.
+    let domain = match config.version {
+        RgaVersion::Rga3 => {
+            if config.core_index == 0 {
+                PowerDomain(22) // RGA30
+            } else {
+                PowerDomain(30) // RGA31
+            }
+        }
+        RgaVersion::Rga2 => PowerDomain(21), // RGA2/VDPU
+    };
+    match rdrive::get_one::<RockchipPM>() {
+        Some(pm) => match pm.lock() {
+            Ok(mut pm) => {
+                if let Err(e) = pm.power_domain_on(domain) {
+                    warn!("RGA power_domain_on({domain:?}) failed: {e:?}");
+                }
+            }
+            Err(e) => warn!("RGA: RockchipPM lock failed: {e:?}"),
+        },
+        None => warn!("RGA: RockchipPM not found; assuming domain already powered"),
+    }
+    // Bus clocks are ungated in enable_rga2_clocks() and the soft-resets are deasserted in
+    // deassert_rga2_resets(), both before any MMIO. The version read succeeds without the reset
+    // deassert (it only needs the APB/hclk interface), but the 2D engine needs the AXI/core
+    // domains out of any residual reset to actually execute a submitted op.
+}
+
+/// Ungate the RGA2 core's CRU bus clocks (hclk, aclk, clk) named by the node's `clocks` DT
+/// property. U-Boot leaves the RGA clocks gated at handoff, so this is the load-bearing step that
+/// makes the version-register read at base+0x28 succeed (otherwise it aborts on a gated bus). The
+/// clock phandles resolve to the RK3588 BSP rk3588-cru.h ids (HCLK/ACLK_RGA2, CLK_RGA2_CORE) whose
+/// gate positions (CLKGATE_CON45 bits 7/8/9) live in the rockchip-soc CRU gate table.
+fn enable_rga2_clocks(info: &FdtInfo<'_>) -> Result<(), OnProbeError> {
+    for clock in &info.clock_lines()? {
+        clock.enable()?;
+    }
     Ok(())
 }
 
+/// Deassert the RGA2 CRU soft-resets named by the node's `resets` DT property so the AXI/core
+/// domains are out of any residual reset before the engine runs. Best-effort and idempotent,
+/// mirroring the JPEG decoder bring-up; symmetric with the RGA2 clock gates at CLKGATE_CON45.
+fn deassert_rga2_resets(info: &FdtInfo<'_>) {
+    let resets = match info.reset_lines() {
+        Ok(resets) => resets,
+        Err(e) => {
+            warn!("RGA2 reset_lines() failed (continuing): {e}");
+            return;
+        }
+    };
+    for reset in &resets {
+        if let Err(e) = reset.deassert() {
+            warn!(
+                "RGA2 reset deassert {:?} ({:#x}) failed (continuing): {e}",
+                reset.name(),
+                reset.id().raw()
+            );
+        }
+    }
+}
+
 fn detect_core_config(info: &FdtInfo<'_>) -> Option<RgaCoreConfig> {
     for compatible in info.node.as_node().compatibles() {
         match compatible {
@@ -73,16 +166,3 @@ fn page_aligned_region(start_raw: usize, size_raw: usize) -> (usize, usize, usiz
     let end = (start_raw + size_raw + page_size - 1) & !(page_size - 1);
     (start, end - start, offset)
 }
-
-fn decode_fdt_irq(interrupts: &[rdrive::probe::fdt::InterruptRef]) -> Option<usize> {
-    let interrupt = interrupts.first()?;
-    match interrupt.specifier.as_slice() {
-        [irq] => Some(*irq as usize),
-        [kind, irq, ..] => match *kind {
-            0 => Some(*irq as usize + 32),
-            1 => Some(*irq as usize + 16),
-            _ => Some(*irq as usize),
-        },
-        _ => None,
-    }
-}

drivers/gpu/rockchip-rga/src/backend/mod.rs

@@ -0,0 +1,46 @@
+//! Generation-specific RGA hardware backends behind one trait (spec §20.1).
+pub mod rga2;
+pub mod rga3;
+
+use crate::{RgaHardwareVersion, RgaVersion, error::Result, operation::RgaOperation};
+
+/// Hardware completion status, polled out of hard-IRQ context in PR-1.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum RgaStatus {
+    Busy,
+    Done,
+    Error,
+}
+
+/// One-shot snapshot of an RGA core's engine state, captured on a timeout so a board run can
+/// localize whether the engine never started, errored, or completed on a different bit.
+#[derive(Debug, Clone, Copy, Default, PartialEq, Eq)]
+pub struct RgaDiag {
+    pub int: u32,
+    pub sys_ctrl: u32,
+    pub cmd_ctrl: u32,
+    pub cmd_base: u32,
+    pub status: u32,
+    pub version: u32,
+    pub cmd_phys: u64,
+}
+
+/// A generation-specific RGA core controller. Owns its MMIO region and DMA context.
+pub trait RgaBackend: Send {
+    fn generation(&self) -> RgaVersion;
+    fn read_version(&self) -> RgaHardwareVersion;
+    /// Returns Ok(()) if this backend can execute `op`, else `RgaError::Unsupported`.
+    fn supports(&self, op: &RgaOperation) -> Result<()>;
+    /// Program registers/command for a validated `op` and start the engine (non-blocking).
+    fn submit(&mut self, op: &RgaOperation) -> Result<()>;
+    /// Poll hardware completion (non-blocking).
+    fn poll(&self) -> RgaStatus;
+    /// Acknowledge/clear the interrupt/status after a completed or errored job.
+    fn ack(&mut self);
+    /// Reset the core for recovery (timeout/fatal error).
+    fn reset(&mut self) -> Result<()>;
+    /// Read-only engine-state snapshot for diagnostics (default zeroed for backends without MMIO).
+    fn diag(&self) -> RgaDiag {
+        RgaDiag::default()
+    }
+}