arch/arm/bk7258: Beken BK7258 support + PSRAM driver + SysTick fix - #344
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yz471686525-eng wants to merge 7 commits into
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Add SoC support for the Beken BK7258, a dual-core Armv8-M STAR-MC1. NuttX runs on CPU0 with the console on UART0 and brings up NSH. Signed-off-by: Yan Zhang <yz471686525@gmail.com>
Add PSRAM controller driver for BK7258: - bk7258_psram.c: PSRAM init, ID detect, data path test, alias detection, access width test - bk7258_psram.h: public API declarations - hardware/bk7258_psram.h: register definitions for PSRAM controller (0x46080000), analog registers, chip IDs - Kconfig: CONFIG_BK7258_PSRAM (default n) - CMakeLists.txt/Make.defs: conditional compilation Supports 3 PSRAM types: - APS6408L (ID 0x8D09, 8MB) - APS128XXO (ID 0x8D08, 16MB) - W955D8MKY (ID 0x1C8F, 4MB) Analog register writes use SPI polling protocol via ana_write()/ana_rmw() - never bare putreg(). Signed-off-by: Zhang Yan <zhangyan68@xiaomi.com>
PSRAM heap (S3): - Add standalone mm heap over PSRAM window (0x60000000) - bk7258_psram_heap_init(): idempotent init via mm_initialize() - bk7258_psram_malloc/calloc/free/meminfo API - Heap does NOT merge with main SRAM heap Throughput fix (S2): - Separate write and read timing (was mixed) - Report KB/s with 1 decimal (was ~0 MB/s due to int truncation) - Show elapsed seconds for each phase Also: fix format warning in bk7258_psram_init(), wrap long comment in bk7258_serial.c. Signed-off-by: Zhang Yan <zhangyan68@xiaomi.com>
- bk7258_psram_memalign(): wraps mm_memalign for DMA-aligned buffer allocation (32/64 byte alignment) - psram_check_no_heap(): helper guard for destructive tests, applied to test/alias/width (prevents heap metadata corruption) - D-cache safety comment: documents cache maintenance requirement if CONFIG_ARMV8M_DCACHE is enabled in the future - Error message: replaced nonexistent psram_heap_deinit with "reboot to reclaim PSRAM" Signed-off-by: Zhang Yan <zhangyan68@xiaomi.com>
up_timer_initialize() wrote the SysTick RELOAD register and then called up_timer_set_lowerhalf(systick_initialize(true, BOARD_SYSTICK_CLOCK, -1)); which looks complete but produced zero timer interrupts. This board does not enable CONFIG_TIMER/CONFIG_TIMER_ARCH, and in that case include/nuttx/timers/arch_timer.h defines up_timer_set_lowerhalf() as an empty macro -- the macro swallows its own argument, so the preprocessor also deleted the systick_initialize() call. SysTick was therefore never enabled and no handler was ever attached: g_system_timer never advanced. The system still booted and NSH still worked, because the console is interrupt driven. The symptoms were sleep() hanging forever and every elapsed-time measurement reading zero (which had silently invalidated the PSRAM throughput figures). Drive the tick directly from the SysTick exception unless the arch_timer lower-half is really built in, and add a compile-time check that the reload value fits the 24-bit RELOAD field. Also declare arm_boardinitialize() in bk7258_start.h: the definition lives in the board layer and bk7258_start.c was calling it without a prototype, so GCC fell back to an implicit int-returning declaration. Verified on BK7258 DevKit: "sleep 10" now takes 10 s (measured with a stopwatch), uptime advances, and CLOCK_MONOTONIC deltas are sane.
mm_memalign() rejects non-powers of two with
if ((alignment & -alignment) != alignment) return NULL;
but 0 passes that test (0 & -0 == 0). Execution then reaches
if (alignment <= MM_ALIGN) { ptr = mm_malloc(...);
DEBUGASSERT(((uintptr_t)ptr) % alignment == 0); }
i.e. a modulo by zero. Filter alignment == 0 and non-powers of two in
bk7258_psram_memalign() so a bad caller gets NULL plus a log line instead
of an assertion or undefined behaviour.
Verified on hardware: "psram align 0 64" and "psram align 48 64" now
report the error and return cleanly; "psram align 32 64",
"psram align 64 614" and "psram fbtest" still return mod=0 buffers.
yz471686525-eng
requested review from
a team,
GUIDINGLI and
xiaoxiang781216
as code owners
August 14, 2026 13:29
Author
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My branch is rebased on the current tip of the target branch, 6 commits Data point that may help narrow this down: nuttx-apps#116 is based on |
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This PR is stale because it has been open 45 days with no activity. Remove stale label or comment or this will be closed in 10 days. |
Author
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Keeping this alive (stale bot) and flagging the CI failure. The failing The BK7258 / PSRAM changes here are confined to |
tanghao-xiaomi
previously approved these changes
Sep 15, 2026
PSRAM init permanently enabled the PSRAM LDO + AHB power domain + peripheral clock and never released them, leaving ~90mA residual after any command that touched PSRAM. Add bk7258_psram_deinit() that reverses init in order (gate clock bit19 -> disable LDO enpsram -> power off AHB PWD_AHBP -> clear init guard) so callers fully power down on exit.
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Adds BK7258 (dual-core Armv8-M STAR-MC1) SoC support with NSH on CPU0/UART0,
a PSRAM controller driver with a standalone heap, and fixes the system tick.
The tick fix is worth calling out: up_timer_initialize() used
but arch_timer.h defines up_timer_set_lowerhalf() as an empty macro when
CONFIG_TIMER_ARCH is off, so the preprocessor discarded the
systick_initialize() call along with it. SysTick was never enabled and no
handler attached: the system booted, NSH worked (interrupt-driven console),
but g_system_timer never advanced -- sleep() hung forever and every elapsed
time measured 0. Now the tick is driven from the SysTick exception unless
the arch_timer lower-half is really built in, with a compile-time check that
the reload value fits the 24-bit RELOAD field.
Tested on BK7258 DevKit: NSH boots, "sleep 10" takes 10 s, PSRAM 16 MB
verified with zero errors (11.3/8.5 MB/s for 32-bit CPU access).