This project covers the implementation of a 6-bit prefix adder, using the Verilog HDL and Qflow suite.
For more details see the detailed documentation (polish).
This repository was archived by the owner on Sep 7, 2024. It is now read-only.
This project covers the implementation of a 6-bit prefix adder, using the Verilog HDL and Qflow suite.
For more details see the detailed documentation (polish).