fix: apply backend timing and instr buffer patches#6
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Extracted combinatorial assignments to `cache_d2h_o.req_ready` into a separate `always @(...)` block in `ip/core/rtl/muntjac_dcache.sv` to improve code organization, along with all corresponding conditional logic. This commit has been created by an automated coding assistant, with human supervision. Prompt: @ip/core/rtl/muntjac_dcache.sv extract combinatorial assignments to `cache_d2h_o.req_ready` into a separate always_comb section, copy all conditional logic too declare a sensitivity list for the new always_comb block create a PR
Fix a fatal zero-delay oscillation detected during simulation by removing the combinatorial dependency of `req_valid` on `req_ready`. The functional units' ready checks have been removed from the structural hazard detection, and a provisional issue signal is now used to assert requests independently of readiness. Stalling logic is maintained via a new `unit_ready` signal combined into pipeline ready checks. This commit has been created by an automated coding assistant, with human supervision. Please fix the bug described in this report: ### Describe the bug When simulating the Muntjac core using an event-driven simulator like Vivado XSIM, the simulation fails immediately at $t=0$ with a fatal iteration limit error: Fatal Error: Iteration limit reached. Possible zero delay oscillation detected where simulation time can not advance. This is caused by a circular combinatorial dependency violating standard valid/ready handshake rules: the backend's req_valid signal combinationally depends on the cache's req_ready signal, but the cache's req_ready signal combinationally depends on req_valid through its internal arbiter. ### Root Cause / Trace 1. muntjac_backend.sv: req_valid depends on mem_ready (req_ready). 2. muntjac_dcache.sv: req_ready depends on req_valid via arbiter. ### Proposed Fix In muntjac_backend.sv, the mem_ready check should be removed from the structural hazard detection for OP_MEM, allowing req_valid to assert independently of req_ready. Stalling the pipeline should be handled by the pipeline stage registers not advancing when req_valid && !req_ready. create PR
Several registers use async reset (always_ff @(posedge clk or negedge rst_ni)) but lack SystemVerilog variable initialization. Event-driven simulators like Vivado xsim evaluate always_comb blocks at time 0 before any clock/reset edge triggers the always_ff blocks, so these registers hold X. This creates a delta cycle oscillation that prevents simulation time from advancing. Adding variable initialization (e.g., `logic valid = 1'b0`) gives these registers defined values from delta 0, matching their async reset values. This has no effect on synthesis. Fixes: lowRISC#4 Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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This PR applies the backend timing and instruction buffer patches from the a200t_examples repository. These changes have been verified with riscv-tests locally using act.