Add mcounteren register#2403
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The changes look all good to me! Just a few minor comments. (I did not look at the two WIP commits about formal)
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I disabled the check of the mcounteren CSR in the formal verification for now. Another reason for the failure of the formal verification was that we ran out of memory on the runner that has twice as many cores but half as much memory available. I'll address this in a separate PR and rebase once merged. |
The set created a random order of the tests. So small modifications or additions to the testlist polluted the diff. Fixing the order in a list makes the output deterministic. I swapped the order of the tests to match the current output order of the testlist to avoid a diff.
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Looks good to me!
I mostly looked at RTL, but the changes in python, C, yaml, etc. look also good to me!
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This PR adds the
mcounterenregister, which has so far been tied to zero and implements the U-mode performance counter aliases. Themcounterenregister can be locked with an external MUBI signal (mcounteren_writable_i).DV:
This PR adds two directed tests:
mcounteren_testgoes through multiple configurations of the mcounteren register and validates that u-mode can only access the ones enabled.mcounteren_lock_testverifies that the mcounteren CSR cannot be modified without themcounteren_writable_isignal being set.To Dos:
dv/uvm/core_ibex/directed_tests/directed_testlist.yamlchanges a lot everytime I regenerate it after even small modifications. This polluted the diff quite a bit. Is this expected?