Fix linter warnings detected by iverilog and add resize(foo,n) support

examples/Makefile

@@ -6,8 +6,8 @@ all:
 ifneq ($(shell which ghdl),)
 	@mkdir -p $(TEMP)
 	@echo "##### Checking examples with GHDL ##############################"
-	ghdl -a --workdir=$(TEMP) signextend.vhd
-	ghdl -a -fsynopsys --workdir=$(TEMP) *.vhd
+	ghdl -a --std=08 --workdir=$(TEMP) signextend.vhd
+	ghdl -a --std=08 -fsynopsys --workdir=$(TEMP) *.vhd
 endif
 
 clean:

examples/agg_risk_demo.vhd

@@ -3,22 +3,19 @@ use ieee.std_logic_1164.all;
 
 entity agg_risk is
     port(
+        a : in std_logic;
+        b : in std_logic;
         y : out std_logic
     );
 end entity agg_risk;
 
 architecture rtl of agg_risk is
-    constant a_c : std_logic_vector(0 downto 0) := "0";
-    constant b_c : std_logic_vector(0 downto 0) := "1";
-    signal y_sel : std_logic;
 begin
     -- Concatenation selector uses op='c' and must be wrapped in Verilog.
-    -- If not wrapped, this becomes "case(a_c,b_c)".
-    with a_c & b_c select
-        y_sel <= '0' when "00",
-                 '1' when "01",
-                 '0' when "10",
-                 '1' when others;
-
-    y <= y_sel;
+    -- If not wrapped, this becomes "case(a,b)".
+    with a & b select
+        y <= '0' when "00",
+             '1' when "01",
+             '0' when "10",
+             '1' when others;
 end architecture rtl;

examples/conv_integer.vhd

@@ -4,8 +4,12 @@ use ieee.std_logic_arith.all;
 
 entity conv_integer_sink is
   port(
-    val_u : in integer;
-    val_i : in integer
+    val_u      : in integer;
+    val_i      : in integer;
+    val_u4     : in integer;
+    val_i4     : in integer;
+    val_u_port : in integer;
+    val_i_port : in integer
   );
 end entity;
 
@@ -27,18 +31,24 @@ entity conv_integer_demo is
 end entity;
 
 architecture rtl of conv_integer_demo is
-  constant s_test_neg : std_logic_vector(7 downto 0) := x"FF";
+  constant s_test_neg : std_logic_vector(7 downto 0) :=  x"FF";
+  signal   sig_4      : std_logic_vector(3 downto 0) := "1111";
 begin
   -- conv_integer should be parsed as CONVFUNC_1 and preserved as expr
   u <= conv_integer(unsigned(s)+1);
   i <= conv_integer(signed(s));
 
-  -- conv_integer in port map, using constant for static expression
+  -- conv_integer in port map: constant/signal/port, signed/unsigned, various widths
   sink_inst : entity work.conv_integer_sink
     port map(
-      -- expected 255
-      val_u => conv_integer(unsigned(s_test_neg)),
-      -- expected -1
-      val_i => conv_integer(signed(s_test_neg))
+      -- constant (param_list): 8-bit
+      val_u      => conv_integer(unsigned(s_test_neg)),  -- expected 255
+      val_i      => conv_integer(signed(s_test_neg)),    -- expected -1
+      -- signal (sig_list): 4-bit
+      val_u4     => conv_integer(unsigned(sig_4)),      -- expected 15
+      val_i4     => conv_integer(signed(sig_4)),        -- expected -1
+      -- port (io_list): 8-bit
+      val_u_port => conv_integer(unsigned(s)),
+      val_i_port => conv_integer(signed(s))
     );
 end architecture;

examples/resize.vhd

@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity resize_demo is
+  port(
+    u4 : in  unsigned(3 downto 0);
+    y8 : out unsigned(7 downto 0);
+    y2 : out unsigned(1 downto 0)
+  );
+end resize_demo;
+
+architecture rtl of resize_demo is
+begin
+  y8 <= resize(u4, 8); -- expect extension to 8 bits
+  y2 <= resize(u4, 2); -- expect truncation to 2 bits
+end rtl;

src/vhd2vl.l

@@ -143,7 +143,7 @@ static void replace_dash(char *s);
 "to_signed" |
 "to_unsigned" |
 "conv_std_logic_vector" |
-"conv_std_ulogic_vector"          { return CONVFUNC_2; }
+"conv_std_ulogic_vector"          { yylval.txt=xstrdup(yytext); return CONVFUNC_2; }
 "to_integer" |
 "conv_integer"                    { yylval.txt=xstrdup(yytext); return CONVFUNC_1; }