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kseerpkseerp
authored
Merge branch 'analogdevicesinc:main' into master
2 parents 3e88ef0 + 893fbaa commit 19d6dcf

8 files changed

Lines changed: 69 additions & 29 deletions

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‎arch/arm/boot/dts/zynq-coraz7s-ad7687-pmdz.dts‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@
6161
vref-supply = <&vref>;
6262
channel@0 {
6363
reg = <0>;
64+
bipolar;
6465
diff-channels = <0 1>;
6566
};
6667
};

‎arch/arm/boot/dts/zynq-coraz7s-ad7984.dts‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@
6161
vref-supply = <&vref>;
6262
channel@0 {
6363
reg = <0>;
64+
bipolar;
6465
diff-channels = <0 1>;
6566
};
6667
};

‎arch/arm64/boot/dts/xilinx/zynqmp-jupiter-sdr.dts‎

Lines changed: 27 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -404,13 +404,6 @@
404404
line-name = "usb-reset";
405405
};
406406

407-
adrv9002_clksrc {
408-
gpio-hog;
409-
gpios = <79 GPIO_ACTIVE_HIGH>;
410-
output-high;
411-
line-name = "adrv9002-clksrc";
412-
};
413-
414407
fan_ctl {
415408
gpio-hog;
416409
gpios = <145 GPIO_ACTIVE_HIGH>;
@@ -600,10 +593,37 @@
600593

601594
#include "adi-adrv9002.dtsi"
602595

596+
/ {
597+
clocks {
598+
adrv9002_clkin2: clock2 {
599+
compatible = "fixed-clock";
600+
601+
clock-frequency = <30720000>;
602+
clock-output-names = "adrv9002_refclk_mux0";
603+
#clock-cells = <0>;
604+
};
605+
};
606+
607+
adrv9002_clk_mux: clk-mux {
608+
#clock-cells = <0>;
609+
compatible = "gpio-mux-clock";
610+
/* 30.72MHz, 38.4MHz */
611+
clocks = <&adrv9002_clkin2>, <&adrv9002_clkin>;
612+
clock-output-names = "adrv9002_ext_refclk";
613+
select-gpios = <&gpio 79 GPIO_ACTIVE_HIGH>;
614+
};
615+
};
616+
617+
&adrv9002_clkin {
618+
clock-output-names = "adrv9002_refclk_mux1";
619+
};
620+
603621
&adc0_adrv9002 {
604622
reset-gpios = <&gpio 81 GPIO_ACTIVE_LOW>;
605623
interrupts = <78 IRQ_TYPE_EDGE_RISING>;
606624

625+
clocks = <&adrv9002_clk_mux>;
626+
607627
adi,channels {
608628
rx@0 {
609629
mux-ctl-gpios = <&gpio 86 GPIO_ACTIVE_HIGH>;

‎drivers/iio/adc/ad_pulsar.c‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -508,7 +508,7 @@ static int ad_pulsar_read_raw(struct iio_dev *indio_dev,
508508
if (ret)
509509
return ret;
510510

511-
if (chan->differential)
511+
if (chan->scan_type.sign == 's')
512512
*val = sign_extend32(*val, adc->info->resolution - 1);
513513

514514
return IIO_VAL_INT;
@@ -523,7 +523,14 @@ static int ad_pulsar_read_raw(struct iio_dev *indio_dev,
523523
if (ret < 0)
524524
return ret;
525525
*val = ret / 1000;
526-
*val2 = adc->info->resolution;
526+
/* When the channel is bipolar, one of the precision
527+
* bits accounts for the sign and we end up with one
528+
* less bit to express voltage magnitude.
529+
*/
530+
if (chan->scan_type.sign == 's')
531+
*val2 = adc->info->resolution - 1;
532+
else
533+
*val2 = adc->info->resolution;
527534

528535
return IIO_VAL_FRACTIONAL_LOG2;
529536
case IIO_TEMP:

‎drivers/iio/dac/ltc2664.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -526,7 +526,7 @@ static int ltc2664_channel_config(struct ltc2664_state *st)
526526
return dev_err_probe(dev, -EINVAL,
527527
"adi,manual-span-operation-config not supported\n");
528528

529-
if (mspan > ARRAY_SIZE(ltc2664_mspan_lut))
529+
if (mspan >= ARRAY_SIZE(ltc2664_mspan_lut))
530530
return dev_err_probe(dev, -EINVAL,
531531
"adi,manual-span-operation-config not in range\n");
532532
}

‎drivers/iio/frequency/ad9783.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -227,8 +227,7 @@ static int ad9783_timing_adjust(struct ad9783_phy *phy)
227227
ret = ad9783_seek(phy);
228228
if (ret < 0)
229229
return ret;
230-
231-
} while (ret > 0 && hld < AD9783_MAX_HLD);
230+
} while ((ret == table[smp][SEEK]) && hld < (AD9783_MAX_HLD - 1));
232231

233232
table[smp][HLD] = hld;
234233
hld = 0;
@@ -250,7 +249,7 @@ static int ad9783_timing_adjust(struct ad9783_phy *phy)
250249
if (ret < 0)
251250
return ret;
252251

253-
} while (ret > 0 && set < AD9783_MAX_SET);
252+
} while ((ret == table[smp][SEEK]) && set < (AD9783_MAX_SET - 1));
254253

255254
table[smp][SET] = set;
256255
}

‎drivers/misc/adi-axi-tdd.c‎

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@
3232
#define ADI_REG_TDD_BURST_COUNT 0x004c
3333
#define ADI_REG_TDD_STARTUP_DELAY 0x0050
3434
#define ADI_REG_TDD_FRAME_LENGTH 0x0054
35-
#define ADI_REG_TDD_SYNC_COUNTER_LOW 0x0058
36-
#define ADI_REG_TDD_SYNC_COUNTER_HIGH 0x005c
35+
#define ADI_REG_TDD_SYNC_PERIOD_LOW 0x0058
36+
#define ADI_REG_TDD_SYNC_PERIOD_HIGH 0x005c
3737
#define ADI_REG_TDD_STATUS 0x0060
3838
#define ADI_REG_TDD_CHANNEL_BASE 0x0080
3939

@@ -233,6 +233,8 @@ static ssize_t adi_axi_tdd_show(struct device *dev,
233233
ret = regmap_read(st->regs, ADI_REG_TDD_STARTUP_DELAY, &data);
234234
if (ret)
235235
return ret;
236+
if (data)
237+
data++;
236238
return adi_axi_tdd_format_ms(st, data, buf);
237239
case ADI_TDD_ATTR_FRAME_LENGTH_RAW:
238240
ret = regmap_read(st->regs, ADI_REG_TDD_FRAME_LENGTH, &data);
@@ -243,18 +245,22 @@ static ssize_t adi_axi_tdd_show(struct device *dev,
243245
ret = regmap_read(st->regs, ADI_REG_TDD_FRAME_LENGTH, &data);
244246
if (ret)
245247
return ret;
248+
if (data)
249+
data++;
246250
return adi_axi_tdd_format_ms(st, data, buf);
247251
case ADI_TDD_ATTR_INTERNAL_SYNC_PERIOD_RAW:
248-
ret = regmap_bulk_read(st->regs, ADI_REG_TDD_SYNC_COUNTER_LOW,
252+
ret = regmap_bulk_read(st->regs, ADI_REG_TDD_SYNC_PERIOD_LOW,
249253
&data64, 2);
250254
if (ret)
251255
return ret;
252256
return sysfs_emit(buf, "%llu\n", data64);
253257
case ADI_TDD_ATTR_INTERNAL_SYNC_PERIOD_MS:
254-
ret = regmap_bulk_read(st->regs, ADI_REG_TDD_SYNC_COUNTER_LOW,
258+
ret = regmap_bulk_read(st->regs, ADI_REG_TDD_SYNC_PERIOD_LOW,
255259
&data64, 2);
256260
if (ret)
257261
return ret;
262+
if (data64)
263+
data64++;
258264
return adi_axi_tdd_format_ms(st, data64, buf);
259265
case ADI_TDD_ATTR_STATE:
260266
ret = regmap_read(st->regs, ADI_REG_TDD_STATUS, &data);
@@ -406,6 +412,8 @@ static int adi_axi_tdd_write_regs(const struct adi_axi_tdd_attribute *attr,
406412
return ret;
407413
if (FIELD_GET(GENMASK_ULL(63, 32), data64))
408414
return -EINVAL;
415+
if (data64)
416+
data64--;
409417
return regmap_write(st->regs, ADI_REG_TDD_STARTUP_DELAY,
410418
(u32)data64);
411419
case ADI_TDD_ATTR_FRAME_LENGTH_RAW:
@@ -419,19 +427,23 @@ static int adi_axi_tdd_write_regs(const struct adi_axi_tdd_attribute *attr,
419427
return ret;
420428
if (FIELD_GET(GENMASK_ULL(63, 32), data64))
421429
return -EINVAL;
430+
if (data64)
431+
data64--;
422432
return regmap_write(st->regs, ADI_REG_TDD_FRAME_LENGTH,
423433
(u32)data64);
424434
case ADI_TDD_ATTR_INTERNAL_SYNC_PERIOD_RAW:
425435
ret = kstrtou64(buf, 0, &data64);
426436
if (ret)
427437
return ret;
428-
return regmap_bulk_write(st->regs, ADI_REG_TDD_SYNC_COUNTER_LOW,
438+
return regmap_bulk_write(st->regs, ADI_REG_TDD_SYNC_PERIOD_LOW,
429439
&data64, 2);
430440
case ADI_TDD_ATTR_INTERNAL_SYNC_PERIOD_MS:
431441
ret = adi_axi_tdd_parse_ms(st, buf, &data64);
432442
if (ret)
433443
return ret;
434-
return regmap_bulk_write(st->regs, ADI_REG_TDD_SYNC_COUNTER_LOW,
444+
if (data64)
445+
data64--;
446+
return regmap_bulk_write(st->regs, ADI_REG_TDD_SYNC_PERIOD_LOW,
435447
&data64, 2);
436448
case ADI_TDD_ATTR_CHANNEL_ENABLE:
437449
ret = kstrtou32(buf, 0, &data);

‎include/dt-bindings/iio/adc/adi,adrv9002.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -41,16 +41,16 @@
4141
#define ADRV9002_GPIO_SIGNAL_ORX_ENABLE_1 0
4242
#define ADRV9002_GPIO_SIGNAL_ORX_ENABLE_2 1
4343
/* AGPIO Signals */
44-
#define ADRV9002_GPIO_SIGNAL_TX1_EXT_FRONTEND_CONTROL 21
45-
#define ADRV9001_GPIO_SIGNAL_TX2_EXT_FRONTEND_CONTROL 22
46-
#define ADRV9001_GPIO_SIGNAL_RX1_EXT_FRONTEND_CONTROL 23
47-
#define ADRV9001_GPIO_SIGNAL_RX2_EXT_FRONTEND_CONTROL 24
48-
#define ADRV9001_GPIO_SIGNAL_EXT_PLL_1_LOCK 25
49-
#define ADRV9001_GPIO_SIGNAL_EXT_PLL_2_LOCK 26
50-
#define ADRV9001_GPIO_SIGNAL_EXT_PLL_1_CE 27
51-
#define ADRV9001_GPIO_SIGNAL_EXT_PLL_2_CE 28
52-
#define ADRV9001_GPIO_SIGNAL_RX_VCO_1_CE 29
53-
#define ADRV9001_GPIO_SIGNAL_RX_VCO_2_CE 30
44+
#define ADRV9002_GPIO_SIGNAL_TX1_EXT_FRONTEND_CONTROL 24
45+
#define ADRV9001_GPIO_SIGNAL_TX2_EXT_FRONTEND_CONTROL 25
46+
#define ADRV9001_GPIO_SIGNAL_RX1_EXT_FRONTEND_CONTROL 26
47+
#define ADRV9001_GPIO_SIGNAL_RX2_EXT_FRONTEND_CONTROL 27
48+
#define ADRV9001_GPIO_SIGNAL_EXT_PLL_1_LOCK 28
49+
#define ADRV9001_GPIO_SIGNAL_EXT_PLL_2_LOCK 29
50+
#define ADRV9001_GPIO_SIGNAL_EXT_PLL_1_CE 30
51+
#define ADRV9001_GPIO_SIGNAL_EXT_PLL_2_CE 31
52+
#define ADRV9001_GPIO_SIGNAL_RX_VCO_1_CE 32
53+
#define ADRV9001_GPIO_SIGNAL_RX_VCO_2_CE 33
5454

5555
/* Frequency hopping modes */
5656
#define ADRV9002_FH_LO_MUX_PREPROCESS 0

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