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kseerpkseerp
authored
Merge branch 'analogdevicesinc:main' into master
2 parents f6627a3 + 0b3d96f commit 3e88ef0

24 files changed

Lines changed: 1609 additions & 374 deletions

‎arch/arm/boot/dts/zynq-coraz7s-adaq4003.dts‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,8 @@
5656
pwms = <&adc_trigger 0 0>;
5757
pwm-names = "cnv";
5858
vref-supply = <&vref>;
59+
adi,high-z-input;
60+
adi,gain-milli = /bits/ 16 <454>;
5961

6062
#address-cells = <1>;
6163
#size-cells = <0>;

‎arch/arm/boot/dts/zynq-zed-adv7511-ad4003.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/*
3+
* Analog Devices AD4003
4+
* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad400x
5+
* https://wiki.analog.com/resources/eval/user-guides/ad400x
6+
*
7+
* hdl_project: <pulsar_adc/zed>
8+
* board_revision: <>
9+
*
10+
* Copyright (C) 2016-2024 Analog Devices Inc.
11+
*/
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/dts-v1/;
13+
14+
#include "zynq-zed.dtsi"
15+
#include "zynq-zed-adv7511.dtsi"
16+
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/ {
18+
adc_vref: regulator-vref {
19+
compatible = "regulator-fixed";
20+
regulator-name = "EVAL 5V Vref";
21+
regulator-min-microvolt = <5000000>;
22+
regulator-max-microvolt = <5000000>;
23+
regulator-always-on;
24+
};
25+
26+
adc_vdd: regulator-vdd {
27+
compatible = "regulator-fixed";
28+
regulator-name = "Eval VDD supply";
29+
regulator-min-microvolt = <1800000>;
30+
regulator-max-microvolt = <1800000>;
31+
regulator-always-on;
32+
};
33+
34+
adc_vio: regulator-vio {
35+
compatible = "regulator-fixed";
36+
regulator-name = "Eval VIO supply";
37+
regulator-min-microvolt = <3300000>;
38+
regulator-max-microvolt = <3300000>;
39+
regulator-always-on;
40+
};
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};
42+
43+
&fpga_axi {
44+
rx_dma: rx-dmac@44a30000 {
45+
compatible = "adi,axi-dmac-1.00.a";
46+
reg = <0x44a30000 0x1000>;
47+
#dma-cells = <1>;
48+
interrupt-parent = <&intc>;
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interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
50+
clocks = <&clkc 17>;
51+
52+
adi,channels {
53+
#size-cells = <0>;
54+
#address-cells = <1>;
55+
56+
dma-channel@0 {
57+
reg = <0>;
58+
adi,source-bus-width = <32>;
59+
adi,source-bus-type = <1>;
60+
adi,destination-bus-width = <64>;
61+
adi,destination-bus-type = <0>;
62+
};
63+
};
64+
};
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66+
axi_pwm_gen: axi-pwm-gen@44b00000 {
67+
compatible = "adi,axi-pwmgen";
68+
reg = <0x44b00000 0x1000>;
69+
label = "adc_conversion_trigger";
70+
#pwm-cells = <2>;
71+
clocks = <&spi_clk>;
72+
};
73+
74+
spi_clk: axi-clkgen@44a70000 {
75+
compatible = "adi,axi-clkgen-2.00.a";
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reg = <0x44a70000 0x10000>;
77+
#clock-cells = <0>;
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clocks = <&clkc 15>, <&clkc 15>;
79+
clock-names = "s_axi_aclk", "clkin1";
80+
clock-output-names = "spi_clk";
81+
};
82+
83+
axi_spi_engine_0: spi@44a00000 {
84+
compatible = "adi,axi-spi-engine-1.00.a";
85+
reg = <0x44a00000 0x1000>;
86+
interrupt-parent = <&intc>;
87+
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
88+
clocks = <&clkc 15 &spi_clk>;
89+
clock-names = "s_axi_aclk", "spi_clk";
90+
num-cs = <1>;
91+
92+
#address-cells = <0x1>;
93+
#size-cells = <0x0>;
94+
95+
ad4003: adc@0 {
96+
compatible = "adi,ad4003";
97+
reg = <0>;
98+
spi-max-frequency = <80000000>;
99+
vdd-supply = <&adc_vdd>;
100+
vio-supply = <&adc_vio>;
101+
vref-supply = <&adc_vref>;
102+
dmas = <&rx_dma 0>;
103+
dma-names = "rx";
104+
clocks = <&spi_clk>;
105+
clock-names = "ref_clk";
106+
pwms = <&axi_pwm_gen 0 0>;
107+
pwm-names = "cnv";
108+
adi,high-z-input;
109+
};
110+
};
111+
};

‎arch/arm/boot/dts/zynq-zed-adv7511-ad4020.dts‎

Lines changed: 32 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -8,19 +8,35 @@
88
* Link: https://github.com/analogdevicesinc/hdl/tree/main/projects/pulsar_adc
99
* board_revision: <>
1010
*
11-
* Copyright (C) 2016-2019 Analog Devices Inc.
11+
* Copyright (C) 2016-2024 Analog Devices Inc.
1212
*/
1313
/dts-v1/;
1414

1515
#include "zynq-zed.dtsi"
1616
#include "zynq-zed-adv7511.dtsi"
1717

1818
/ {
19-
vref: regulator-vref {
19+
adc_vref: regulator-vref {
2020
compatible = "regulator-fixed";
21-
regulator-name = "fixed-supply";
22-
regulator-min-microvolt = <2500000>;
23-
regulator-max-microvolt = <2500000>;
21+
regulator-name = "EVAL 5V Vref";
22+
regulator-min-microvolt = <5000000>;
23+
regulator-max-microvolt = <5000000>;
24+
regulator-always-on;
25+
};
26+
27+
adc_vdd: regulator-vdd {
28+
compatible = "regulator-fixed";
29+
regulator-name = "Eval VDD supply";
30+
regulator-min-microvolt = <1800000>;
31+
regulator-max-microvolt = <1800000>;
32+
regulator-always-on;
33+
};
34+
35+
adc_vio: regulator-vio {
36+
compatible = "regulator-fixed";
37+
regulator-name = "Eval VIO supply";
38+
regulator-min-microvolt = <3300000>;
39+
regulator-max-microvolt = <3300000>;
2440
regulator-always-on;
2541
};
2642
};
@@ -30,6 +46,7 @@
3046
compatible = "adi,axi-dmac-1.00.a";
3147
reg = <0x44a30000 0x1000>;
3248
#dma-cells = <1>;
49+
interrupt-parent = <&intc>;
3350
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
3451
clocks = <&clkc 17>;
3552

@@ -47,7 +64,7 @@
4764
};
4865
};
4966

50-
adc_trigger: pwm@44b00000 {
67+
axi_pwm_gen: axi-pwm-gen@44b00000 {
5168
compatible = "adi,axi-pwmgen";
5269
reg = <0x44b00000 0x1000>;
5370
label = "adc_conversion_trigger";
@@ -69,7 +86,7 @@
6986
reg = <0x44a00000 0x1000>;
7087
interrupt-parent = <&intc>;
7188
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
72-
clocks = <&clkc 15>, <&spi_clk>;
89+
clocks = <&clkc 15 &spi_clk>;
7390
clock-names = "s_axi_aclk", "spi_clk";
7491
num-cs = <1>;
7592

@@ -79,17 +96,17 @@
7996
ad4020: adc@0 {
8097
compatible = "adi,ad4020";
8198
reg = <0>;
82-
spi-max-frequency = <102000000>;
83-
84-
clocks = <&spi_clk>;
85-
clock-names = "ref_clk";
99+
spi-max-frequency = <80000000>;
100+
vdd-supply = <&adc_vdd>;
101+
vio-supply = <&adc_vio>;
102+
vref-supply = <&adc_vref>;
86103
dmas = <&rx_dma 0>;
87104
dma-names = "rx";
88-
pwms = <&adc_trigger 0 0>;
105+
clocks = <&spi_clk>;
106+
clock-names = "ref_clk";
107+
pwms = <&axi_pwm_gen 0 0>;
89108
pwm-names = "cnv";
90-
91-
vref-supply = <&vref>;
92-
#io-channel-cells = <1>;
109+
adi,high-z-input;
93110
};
94111
};
95112
};

‎arch/arm/boot/dts/zynq-zed-adv7511-ad4030-24.dts‎

Lines changed: 127 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,127 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Analog Devices AD4630-24
4+
*
5+
* hdl_project: <ad4630_fmc/zed>
6+
* board_revision: <B>
7+
*
8+
* Copyright (C) 2023 Analog Devices Inc.
9+
*/
10+
/dts-v1/;
11+
12+
#include "zynq-zed.dtsi"
13+
#include "zynq-zed-adv7511.dtsi"
14+
#include <dt-bindings/gpio/gpio.h>
15+
#include <dt-bindings/pwm/pwm.h>
16+
17+
/ {
18+
vref: regulator-vref {
19+
compatible = "regulator-fixed";
20+
regulator-name = "fixed-supply";
21+
regulator-min-microvolt = <5000000>;
22+
regulator-max-microvolt = <5000000>;
23+
regulator-always-on;
24+
};
25+
26+
vdd_1_8: regulator-vdd-1-8 {
27+
compatible = "regulator-fixed";
28+
regulator-name = "fixed-supply";
29+
regulator-min-microvolt = <1800000>;
30+
regulator-max-microvolt = <1800000>;
31+
regulator-always-on;
32+
};
33+
34+
vio: regulator-vio {
35+
compatible = "regulator-fixed";
36+
regulator-name = "fixed-supply";
37+
regulator-min-microvolt = <1800000>;
38+
regulator-max-microvolt = <1800000>;
39+
regulator-always-on;
40+
};
41+
42+
clocks {
43+
cnv_ext_clk: ext-clk {
44+
#clock-cells = <0x0>;
45+
compatible = "fixed-clock";
46+
clock-frequency = <100000000>;
47+
clock-output-names = "cnv_ext_clk";
48+
};
49+
};
50+
};
51+
52+
&fpga_axi {
53+
rx_dma: rx-dmac@44a30000 {
54+
compatible = "adi,axi-dmac-1.00.a";
55+
reg = <0x44a30000 0x1000>;
56+
#dma-cells = <1>;
57+
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
58+
clocks = <&clkc 15>;
59+
60+
adi,channels {
61+
#size-cells = <0>;
62+
#address-cells = <1>;
63+
64+
dma-channel@0 {
65+
reg = <0>;
66+
adi,source-bus-width = <64>;
67+
adi,source-bus-type = <1>;
68+
adi,destination-bus-width = <64>;
69+
adi,destination-bus-type = <0>;
70+
};
71+
};
72+
};
73+
74+
spi_clk: axi-clkgen@0x44a70000 {
75+
compatible = "adi,axi-clkgen-2.00.a";
76+
reg = <0x44a70000 0x10000>;
77+
#clock-cells = <0>;
78+
clocks = <&clkc 15>, <&clkc 15>;
79+
clock-names = "s_axi_aclk", "clkin1";
80+
clock-output-names = "spi_clk";
81+
};
82+
83+
axi_pwm_gen: axi-pwm-gen@ {
84+
compatible = "adi,axi-pwmgen";
85+
reg = <0x44b00000 0x1000>;
86+
label = "ad463x_cnv";
87+
#pwm-cells = <2>;
88+
clocks = <&cnv_ext_clk>;
89+
90+
};
91+
92+
axi_spi_engine: spi@44a00000 {
93+
compatible = "adi-ex,axi-spi-engine-1.00.a";
94+
reg = <0x44a00000 0x1FF>;
95+
interrupt-parent = <&intc>;
96+
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
97+
clocks = <&clkc 15>, <&spi_clk>;
98+
clock-names = "s_axi_aclk", "spi_clk";
99+
num-cs = <1>;
100+
101+
#address-cells = <0x1>;
102+
#size-cells = <0x0>;
103+
104+
ad4030: ad4030@0 {
105+
compatible = "adi,ad4030-24";
106+
reg = <0>;
107+
vdd-supply = <&vref>;
108+
vdd_1_8-supply = <&vdd_1_8>;
109+
vio-supply = <&vio>;
110+
vref-supply = <&vref>;
111+
spi-max-frequency = <80000000>;
112+
reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;
113+
114+
adi,lane-mode = <0>;
115+
adi,clock-mode = <0>;
116+
adi,out-data-mode = <0>;
117+
118+
adi,spi-trigger;
119+
clocks = <&cnv_ext_clk>;
120+
clock-names = "trigger_clock";
121+
dmas = <&rx_dma 0>;
122+
dma-names = "rx";
123+
pwm-names = "spi_trigger", "cnv";
124+
pwms = <&axi_pwm_gen 0 0>, <&axi_pwm_gen 1 0>;
125+
};
126+
};
127+
};

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