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chips: 16 market variants — variant-aware 3D, data-flow loop, scale visualizations - #14
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- Data flow: toggleable animated packet loop with 4 captioned stages per chip (CPU/GPU/DPU), rewritten across ELI5/15/Pro/Expert, bounded particle pool, active-stage highlighting, Genoa-X/B200 topology overrides, window.__chipVariant / refreshFlowPaths integration contract. - Scale: new section below the hero with its own canvas and Solo/Node/ Rack/Cluster preset pills. Distinct NVLink (teal), PCIe (amber), IB/Ethernet (blue) links with animated packets; per-preset captions rewrite with explanation depth; each preset carries the local-vs- large-scale contrast and the why-every-node-gets-a-DPU rationale. - QA: headless Chromium screenshots (hero, flow mode, all scale presets), zero console errors (only artifact is the file:// favicon 404; production path /assets/favicon.svg exists).
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…yclopedia - 16 selectable market variants (6 CPU, 5 GPU, 5 DPU) with per-variant 3D geometry: Genoa-X V-Cache tiers, Granite Rapids EMIB tiles, M4 Max monolithic SoC + unified memory, H100 NVL twin cards, B200 dual-die + NV-HBI, RTX 4090 GDDR6X + cooler, MI300X 8-XCD chiplet ring, E2100 P4 pipeline, Elba 144-MPU grid, OCTEON 10 inline-AI block - Variant-aware part encyclopedia (PVAR), comparison/diff copy (VDIFF), glance table, model labels, and 'what changed' cards at all 4 depths - Per-variant data-flow paths and stage captions; flow particles and highlights now track the actual silicon of every variant - Provenance: per-variant sources; geometry labeled schematic/estimated Verified: inline script syntax-clean; data-layer + flow-override test suites pass (16 variants x 4 stages x 4 depths).
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The /chips/ visualization is now variant-first: 16 real market products across CPU/GPU/DPU, each with its own physical 3D geometry, data-flow path, and encyclopedia copy. Page-only scope — only
chips/index.htmlchanged.Market variants (16, selectable via pills)
Physical differences called out in 3D — per-variant dynamic builders: Genoa-X's 12 stacked V-Cache tiers rising above the CCDs, Granite Rapids' EMIB compute/SoC tiles, M4 Max monolithic SoC + unified LPDDR5X, H100 NVL twin cards + 3 NVLink bridges, B200 dual dies + NV-HBI, RTX 4090 GDDR6X ring + triple-fan cooler, MI300X 8-XCD chiplet ring + 4 IODs, E2100 P4 pipeline, Elba's 144-MPU grid, OCTEON 10 inline-AI block.
Data streaming through the chip — toggleable animated packet loop (bounded 150-particle pool) with 4 auto-advancing captioned stages per chip. Flow paths and stage captions are now variant-aware: every variant's particles follow its own silicon and highlights track its real blocks (e.g. GDDR6X on the 4090, XCDs on MI300X, SoC tiles on Granite Rapids). Captions rewrite across ELI5 / 15 / Pro / Expert.
Large-scale vs local — Solo / Node / Rack / Cluster scale visualization with animated PCIe, NVLink/NVSwitch, and InfiniBand/Ethernet links: chips linked into networks for large-scale computing vs local model training.
Variant-aware encyclopedia — part entries, component-diff copy, glance table, model labels, pinned 'what changed' cards, and pulse highlights all follow the selected variant at all four explanation depths.
Provenance — headline specs verified against vendor/press sources (Sep 2026), per-variant source list on-page. Exploded geometry is schematic/estimated (labeled as such) — vendors don't publish package CAD.
Verification — inline script syntax-clean; data-layer and flow-override suites pass (16 variants × 4 stages × 4 depths; every stage's highlighted parts exist in the part index). Teardown disposes geometries/materials and clears raycast/label references on swap.
Review-ready. Not merging without explicit approval.