Bare-metal RV32 support and a qemu smoke test

[pawlex]

Runs the i386 core on a bare-metal 32-bit RISC-V target — no OS, no heap,
no host libc beyond picolibc. Verified under qemu-system-riscv32.

make -C rv32 run

Default builds are unaffected. With no new macros defined and on a
non-RISC-V target, i386.c compiles exactly as before — the three
changes are all behind guards.

Changes to i386.c

change	guard	why
x87 becomes opt-out	-DI386_DISABLE_FPU	The integer core uses no floating point; fpu.c holds the project's only FP references. Dropping it avoids pulling soft-float into targets without an FPU. Stubs for the disabled case already existed.
get_nticks() uses rdcycle/rdcycleh	#if defined(__riscv) && __riscv_xlen == 32	Bare metal has no clock_gettime. Feeds the emulated RDTSC; counting CPU cycles is arguably closer to real x86 TSC semantics than the host build's nanoseconds.
two mallocs become static	-DTINY386_STATIC_ALLOC	No heap. CPUI386 512 B + 12 KB TLB. Assumes a single CPU instance.

Plus baremetal_stubs.c for usleep(), called on the idle path at
i386.c:5030. Nothing else was needed — picolibc's semihosting crt0
supplies stdout/stderr/_exit, so no fprintf/abort stubs and
printf works under qemu.

Smoke test

rv32/ holds a small flat-32-bit payload whose every emitted value is
computed rather than constant, so the output can't be produced by
anything but real execution — squares via IMUL and a decrementing ECX
through LOOP, a memory round-trip surviving an XOR EAX,EAX clobber,
and a byte store read back with MOVZX.

   OUT32 port=0x080 <= 0x00000019     25 = 5^2
   ...
   OUT32 port=0x080 <= 0xa5a5a5a5     memory round-trip
   OUT32 port=0x080 <= 0x00000042     byte store + movzx
   OUT32 port=0x080 <= 0xdeadbeef     end marker
RESULT: PASS

Footprint

-Os -DNDEBUG, FPU off, picolibc:

target	.text
rv32im	159,361 B
rv32imc	119,917 B
x86-64 (host reference, with x87)	140,422 B

plus ~12 KB writable state excluding guest RAM.

Why the Makefile defaults to rv32im

Compressed instructions are 25% smaller, which looks decisive until the
core running it is measured. Tested against VexRiscv on a Lattice
ECP5 LFE5U-85F (yosys 0.68 + nextpnr-ecp5, out-of-context):

variant	LUT4	Fmax
VexRiscv_Full	3,908	96.55 MHz
VexRiscv_IMAC (RVC)	4,533	57.43 MHz

The decompressor lands on the critical path — 40% of the clock for 25%
of the code. Smaller code helps I-cache hit rate but would need to be
worth 68% to break even. Override with make ARCH=rv32imc where
compressed support is cheap. rv32/README.md has the full variant table.

Not covered

rdcycle is unexercised (the payload never runs RDTSC), interrupts are
untouched, and the payload is flat 32-bit via cpui386_reset_pm() rather
than real mode.

[hchunhui]

There is no longer a hardcoded I386_ENABLE_FPU in the current main branch (see commit 5805950).

For other changes, consider adding clock_gettime() and malloc() (implemented as a simple bump allocator) in baremetal_stubs.c.

[pawlex]

understood -- realized after PR this was working with a stale branch. If there is interest from upstream, I will re-generate after integration is complete.