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arch-amdgpu: improve page-walk caching and TLB coalescing #2

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arch-amdgpu: improve page-walk caching and TLB coalescing #2

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arch-amdgpu: add a neighbour PWC and configurable walk fetch width
Basemism Sep 2, 2026
85e8bdd
arch-amdgpu: improve large-page TLB coalescing and prediction
Basemism Sep 2, 2026
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11 changes: 11 additions & 0 deletions configs/common/GPUTLBConfig.py
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,9 @@ def TLB_constructor(options, level, gpu_ctrl=None, full_system=False):
if full_system:
constructor_call = "VegaGPUTLB(\
gpu_device = gpu_ctrl, \
walker = VegaPagetableWalker(\
pwc_fetch_bytes = getattr(\
options, 'pwc_fetch_bytes', 64)), \
size = options.L%(level)dTLBentries, \
assoc = options.L%(level)dTLBassoc, \
hitLatency = options.L%(level)dAccessLatency,\
Expand Down Expand Up @@ -212,6 +215,14 @@ def config_tlb_hierarchy(
system.%s_tlb[%d].cpu_side_ports[0]"
% (name, index, name, index)
)
# Give each Vega coalescer a handle to the TLB it feeds so the
# L3 coalescer can read that TLB's line-coalescing predictor.
if full_system:
exec(
"system.%s_coalescer[%d].downstream_tlb = \
system.%s_tlb[%d]"
% (name, index, name, index)
)

# Connect the cpuSidePort of all the coalescers in level 1
# < Modify here if you want a different configuration >
Expand Down
11 changes: 8 additions & 3 deletions configs/example/gpufs/system/system.py
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Original file line number Diff line number Diff line change
Expand Up @@ -115,7 +115,10 @@ def makeGpuFSSystem(args):

# This arbitrary address is something in the X86 I/O hole
hsapp_gpu_map_paddr = 0xE0000000
hsapp_pt_walker = VegaPagetableWalker()
pwc_fetch_bytes = getattr(args, "pwc_fetch_bytes", 64)
hsapp_pt_walker = VegaPagetableWalker(
pwc_fetch_bytes=pwc_fetch_bytes
)
gpu_hsapp = HSAPacketProcessor(
pioAddr=hsapp_gpu_map_paddr,
numHWQueues=args.num_hw_queues,
Expand All @@ -127,7 +130,7 @@ def makeGpuFSSystem(args):
if args.exit_after_gpu_kernel > -1:
dispatcher_exit_events = True
dispatcher = GPUDispatcher(kernel_exit_events=dispatcher_exit_events)
cp_pt_walker = VegaPagetableWalker()
cp_pt_walker = VegaPagetableWalker(pwc_fetch_bytes=pwc_fetch_bytes)
target_kernel = args.skip_until_gpu_kernel
gpu_cmd_proc = GPUCommandProcessor(
hsapp=gpu_hsapp,
Expand Down Expand Up @@ -210,7 +213,9 @@ def makeGpuFSSystem(args):
sdma_pt_walkers = []
sdma_engines = []
for sdma_idx in range(num_sdmas):
sdma_pt_walker = VegaPagetableWalker()
sdma_pt_walker = VegaPagetableWalker(
pwc_fetch_bytes=pwc_fetch_bytes
)
sdma_engine = SDMAEngine(
walker=sdma_pt_walker,
mmio_base=sdma_bases[sdma_idx],
Expand Down
23 changes: 23 additions & 0 deletions src/arch/amdgpu/vega/VegaGPUTLB.py
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Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,24 @@ class VegaPagetableWalker(ClockedObject):
)
enable_pwc = Param.Bool(True, "Enable page walk cache")

# Second PWC for caching neighbouring final-level entries fetched from
# the same page-table memory fetch. The fetch width is controlled by
# pwc_fetch_bytes.
neighbour_pwc_entries = Param.Int(256, "Neighbour PWC entries")
neighbour_pwc_replacement_policy = Param.BaseReplacementPolicy(
LRURP(), "Replacement policy of the neighbour PWC"
)
neighbour_pwc_indexing_policy = Param.VegaPWCIndexingPolicy(
VegaPWCIndexingPolicy(
entries=Parent.neighbour_pwc_entries,
assoc=Parent.neighbour_pwc_entries,
),
"Indexing policy of the neighbour PWC",
)

pwc_fetch_bytes = Param.Unsigned(
128, "Page-walk fetch granularity in bytes"
)

class VegaGPUTLB(ClockedObject):
type = "VegaGPUTLB"
Expand Down Expand Up @@ -106,3 +124,8 @@ class VegaTLBCoalescer(ClockedObject):
cpu_side_ports = VectorResponsePort("Port on side closer to CPU/CU")
mem_side_ports = VectorRequestPort("Port on side closer to memory")
disableCoalescing = Param.Bool(False, "Dispable Coalescing")
downstream_tlb = Param.VegaGPUTLB(
NULL,
"The TLB this coalescer feeds; used by the L3 coalescer to read the "
"line-coalescing predictor",
)
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