Name		Name	Last commit message	Last commit date
SCMP		SCMP
README.md		README.md
forwarding_unit_wvf.PNG		forwarding_unit_wvf.PNG
hazard_detect_unit_wvf.PNG		hazard_detect_unit_wvf.PNG
pipeline.PNG		pipeline.PNG
screenshot of top level entity.PNG		screenshot of top level entity.PNG
top_entity_block.PNG		top_entity_block.PNG

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Pipelined-MIPS-processor

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A hardware implementation of a 32-bit MIPS processor designed using VHDL. This project focuses on the fundamental principles of computer architecture, featuring a multi-cycle pipelined data path.

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