riscv: add prefetch optimization for doubleFast compressor#4668
riscv: add prefetch optimization for doubleFast compressor#4668Felix-Gong wants to merge 1 commit into
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Extend the aarch64 PREFETCH_L1(ip+256) optimization to RISC-V 64-bit in both ZSTD_compressBlock_doubleFast_noDict_generic and ZSTD_compressBlock_doubleFast_dictMatchState_generic functions. The prefetch targets sequential data access patterns in the compression loop, improving cache locality for RISC-V processors. Performance results on RISC-V 64-bit (RV64GC): - Random data compression: +9.0% (337.3 -> 367.6 MB/s) - Random data decompression: +8.0% (2763.0 -> 2983.9 MB/s) - Zero data: no regression Tested on RISC-V 64-bit server with GCC 15.1.
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Summary
PREFETCH_L1(ip+256)to RISC-V via macro guardzstd_double_fast.cChanges
Extended the architecture guard from
#if defined(__aarch64__)to#if defined(__aarch64__) || (defined(__riscv) && (__riscv_xlen == 64))in two locations:ZSTD_compressBlock_doubleFast_noDict_generic(line 236)ZSTD_compressBlock_doubleFast_dictMatchState_generic(line 451)Performance Results (RISC-V 64-bit, RV64GC)
Testing
zstd -bNotes