Mini RISC-V SoC with UART and GPIO (SKY130)

📌 Overview

This project implements a minimal RISC-V System-on-Chip (SoC) using the SKY130 process node and the OpenLane flow.
The SoC integrates:

• PicoRV32 RISC-V CPU core
• UART peripheral for serial communication
• GPIO peripheral for simple input/output

The design demonstrates how lightweight open-source SoCs can be built with reusable IP blocks and fabricated using open-source flows.

---

🚀 Features

• RV32I-compatible RISC-V CPU (PicoRV32)
• Memory-mapped UART (TX/RX)
• Memory-mapped GPIO registers
• Synthesizable for SKY130 with OpenLane

---

🛠️ Tools Used

• Quartus / ModelSim → RTL coding & simulation
• OpenLane + SKY130 PDK → ASIC synthesis & layout
• Icarus Verilog + GTKWave (optional) → open-source simulation

---

✅ Deliverables

• Verilog RTL and testbenches
• Simulation waveforms (ModelSim)
• OpenLane synthesis, STA, and layout reports
• Documentation (this README + license)

---

📜 License

Released under the MIT License.