reset out float

[M0stafaRady]

Frigate GL simualtion failed since resetb_out_l is float it should be connected to resetb_in_h through level shifter.

frigate_analog/verilog/frigate_timing_frontend.v

Line 26 in 84f5d21

output wire resetb_out_l, // NOTE: 1.8V domain signal

[RTimothyEdwards]

@M0stafaRady : The level shifter was moved from the SoC into the timing frontend. Apparently the schematic and layout were updated but the verilog was not. The verilog is missing the level shifter. I will fix this.

[RTimothyEdwards]

@M0stafaRady : Fixed by PR #3

[M0stafaRady]

@RTimothyEdwards
I'm getting error that sky130_fd_sc_hvl__decap4 does not exist in my pdk 0c1df35fd535299ea1ef74d1e9e15dedaeb34c32 (2024.12.11). Do you know if this is a new cell or a removed one ?

[passant5]

@RTimothyEdwards I think it should be sky130_fd_sc_hvl__decap_4 here:

frigate_analog/verilog/xres_buf.v

Line 75 in ed0f5f9

sky130_fd_sc_hvl__decap4 x4[1:0] (

[RTimothyEdwards]

@passant5 : Yes, indeed. Fixed.