[wishbone] burst mode: ACK is independent of STB requirement

examples/wishbone/wishbone.prot

@@ -130,13 +130,12 @@ prot read<self: Wishbone>(mask: u4, addr: u32, data: u32) {
 prot write_burst_const<self: Wishbone>(mask: u4, addr: u32, data: [u32]+) {
     // no RST
     self.RST := 1'b0;
+
     // constant burst cycle (in which case bte is don't care)
     self.CTI := 3'b001;
     self.BTE := X;
 
-    // in our simple version, we always drive cyc and stb together
     self.CYC := 1'b1;
-    self.STB := 1'b1;
 
     // we are writing
     self.WE := 1'b1;
@@ -146,6 +145,8 @@ prot write_burst_const<self: Wishbone>(mask: u4, addr: u32, data: [u32]+) {
     self.SEL := mask;
 
     for d in data {
+        // set STB for at least one cycle
+        self.STB := 1'b1;
         self.DAT_O := d;
 
         // indicate end of cycle for last item
@@ -156,6 +157,12 @@ prot write_burst_const<self: Wishbone>(mask: u4, addr: u32, data: [u32]+) {
         // wait for ack
         while self.ACK == 1'b0 {
             step();
+            // after the first cycle, STB does not have to remain at one
+            // OBSERVATION 4.00:
+            // "[The server] can use the [CTI_I()] signals to determine the response for the next cycle.
+            //  But it cannot determine the state of [STB_I] for the next cycle,
+            //  therefore it must generate the response independent of [STB_I]."
+            self.STB := X;
         }
 
         // acknowledge is now true for one cycle

interp/src/main.rs

@@ -61,6 +61,11 @@ struct Cli {
     /// Skips the static checks for step/fork errors.
     #[arg(long)]
     skip_static_step_fork_checks: bool,
+
+    /// Optimize the underlying transition system before simulation.
+    /// This might change the combinational dependencies.
+    #[arg(long)]
+    simplify_rtl: bool,
 }
 
 /// Examples (enables all tracing logs):
@@ -123,6 +128,7 @@ fn main() -> anyhow::Result<()> {
         cli.module,
         protocols_handler,
         cli.skip_static_step_fork_checks,
+        cli.simplify_rtl,
     )?;
 
     // Nikil says we have to do this step in order to convert

protocols/src/errors.rs

@@ -736,34 +736,11 @@ impl DiagnosticEmitter {
                 );
             }
             EvaluationError::ForbiddenPortRead {
-                port_name,
                 unassigned_inputs,
                 expr_id,
+                ..
             } => {
-                let input_names: Vec<_> = unassigned_inputs
-                    .iter()
-                    .map(|(name, _)| format!("'{}'", name))
-                    .collect();
-                // Inputs with no stmt_id were never explicitly assigned (implicit DontCare at initialization)
-                let implicit_names: Vec<_> = unassigned_inputs
-                    .iter()
-                    .filter(|(_, stmt_id)| stmt_id.is_none())
-                    .map(|(name, _)| format!("'{}'", name))
-                    .collect();
-                let implicit_note = if implicit_names.is_empty() {
-                    String::new()
-                } else {
-                    format!(
-                        " ({} initialized to DontCare and were never assigned a concrete value)",
-                        implicit_names.join(", ")
-                    )
-                };
-                let main_message = format!(
-                    "Output '{}' depends on input(s) {} which do not have assigned values{}",
-                    port_name,
-                    input_names.join(", "),
-                    implicit_note
-                );
+                let main_message = format!("{error}");
                 let stmt_labels: Vec<_> = unassigned_inputs
                     .iter()
                     .filter_map(|(name, stmt_id)| {

protocols/src/setup.rs

@@ -63,8 +63,13 @@ pub fn setup_test_environment(
     top_module: Option<String>,
     handler: &mut DiagnosticHandler,
     skip_static_step_fork_checks: bool,
+    simplify_rtl: bool,
 ) -> anyhow::Result<TestEnv> {
-    let (ctx, sys) = create_sim_context(verilog_paths, top_module);
+    let (mut ctx, mut sys) = create_sim_context(verilog_paths, top_module);
+    if simplify_rtl {
+        patronus::system::transform::replace_anonymous_inputs_with_zero(&mut ctx, &mut sys);
+        patronus::system::transform::simplify_expressions(&mut ctx, &mut sys);
+    }
     let parsed = frontend(transaction_filename, handler, skip_static_step_fork_checks)?;
     Ok((parsed, ctx, sys))
 }