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Improve top-level module guessing method in base runner class#8228

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kbieganski merged 1 commit intochipsalliance:masterfrom
Arya-Golkari:guess_top
Apr 20, 2026
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Improve top-level module guessing method in base runner class#8228
kbieganski merged 1 commit intochipsalliance:masterfrom
Arya-Golkari:guess_top

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@Arya-Golkari
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Currently, the BaseRunner method guess_top_module just greps for the first module in the file if the top-level module is not passed as a parameter. However, most tests follow a helpful naming convention: top-level modules are conveniently named top. This PR modifies guess_top_module to exploit this pattern.

This PR was motivated by "The force and release procedural statements" test, where the top-level module is currently guessed to be flop instead of top. This has led CIRCT-Verilog to erroneously pass this test.

I'd really appreciate help from reviewers! @fabianschuiki @kbieganski

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linux-foundation-easycla Bot commented Feb 27, 2026

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  • ✅ login: Arya-Golkari / name: Arya-Golkari (c2e746e)

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@tobiasgrosser tobiasgrosser left a comment

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LGTM

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@fabianschuiki fabianschuiki left a comment

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Nice, LGTM!

@tobiasgrosser
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@wsnyder , @kbieganski, any chance we can get this merged?

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@Arya-Golkari, can you rebase this as we now fixed the build failure on main.

@Arya-Golkari
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@tobiasgrosser I've now rebased; sorry for the delay.

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Changes In Tests

Tool New Failures New Passes Added Removed Not Affected
Yosys 0 1 0 0 4730
tree_sitter_systemverilog 2 18 0 0 4896
Odin 0 0 0 0 5009
circt_verilog 48 23 0 0 5001
Verible 0 0 0 0 4918
Verilator 0 0 0 0 5077
yosys_slang 0 0 0 0 4278
sv_parser 0 0 0 0 5009
tree_sitter_verilog 0 0 0 0 4918
SynligYosys 1 1 0 0 4728
Icarus 0 0 0 0 5076
Surelog 0 0 0 0 5072
Sv2v_zachjs 0 0 0 0 5072
moore_parse 0 0 0 0 4918
VeribleExtractor 0 0 0 0 4918
moore 106 1066 0 0 3837
Slang_parse 0 0 0 0 5009
Slang 0 0 0 0 5073

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@kbieganski kbieganski merged commit 98b041e into chipsalliance:master Apr 20, 2026
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4 participants