Solve naming conflict with Yosys

[leviathanch]

Yosys and other synthesis tools already have internal ALU blocks which collide with a module named ALU

[linux-foundation-easycla]

• ❌ The email address for the commit (4eaca97) is not linked to the GitHub account, preventing the EasyCLA check. Consult this Help Article and GitHub Help to resolve. (To view the commit's email address, add .patch at the end of this PR page's URL.) For further assistance with EasyCLA, please submit a support request ticket.

[jerryz123]

@leviathanch you need to amend that commit to include a email that is associated with your Github account, such that the EasyCLA can work.

[jackkoenig]

I think this change is pragmatic, but tools like Yosys really should handle collisions with user-defined modules in ways that don't require you to rename your module.

[jackkoenig]

The real bug is the lack of packages/namespaces in Verilog though...