RP2350: adding complete bsp support

configs/rpi_pico2w_defconfig

@@ -0,0 +1,6 @@
+# SPDX-FileCopyrightText: 2026 H2Lab Development Team
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARCH_MCU_RP2350=y
+CONFIG_STANDALONE_MODE=y
+# CONFIG_WITH_SMP_SUPPORT is not set

dts/examples/rpi_pico2w.dts

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2026 H2Lab Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <rpi/pico/rp2350.dtsi>
+
+/ {
+	chosen {
+		sentry,debug_stdout = <&uart0>;
+		sentry,kernelram_section = <&kernel_ram>;
+		sentry,idleram_section = <&idle_ram>;
+		sentry,kernelcode_section = <&kernel_code>;
+		sentry,idlecode_section = <&idle_code>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		kernel_code: kernel_code@1000000 {
+			reg = <0x1000000 0xb000>;
+			compatible = "sentry,memory-pool";
+		};
+
+		idle_code: idle_code@100c000 {
+			reg = <0x100c000 0x500>;
+			compatible = "sentry,memory-pool";
+		};
+
+		kernel_ram: kernel_memory@20000000 {
+			reg = <0x20000000 0x2000>;
+			compatible = "sentry,memory-pool";
+		};
+
+		idle_ram: idle_memory@20004000 {
+			reg = <0x20004000 0x200>;
+			compatible = "sentry,memory-pool";
+		};
+	};
+
+	pico_header: connector {
+		compatible = "raspberrypi,pico-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 0 0>,    /* GP0 */
+			<1 0 &gpio0 1 0>,       /* GP1 */
+			<2 0 &gpio0 2 0>,       /* GP2 */
+			<3 0 &gpio0 3 0>,       /* GP3 */
+			<4 0 &gpio0 4 0>,       /* GP4 */
+			<5 0 &gpio0 5 0>,       /* GP5 */
+			<6 0 &gpio0 6 0>,       /* GP6 */
+			<7 0 &gpio0 7 0>,       /* GP7 */
+			<8 0 &gpio0 8 0>,       /* GP8 */
+			<9 0 &gpio0 9 0>,       /* GP9 */
+			<10 0 &gpio0 10 0>,     /* GP10 */
+			<11 0 &gpio0 11 0>,     /* GP11 */
+			<12 0 &gpio0 12 0>,     /* GP12 */
+			<13 0 &gpio0 13 0>,     /* GP13 */
+			<14 0 &gpio0 14 0>,     /* GP14 */
+			<15 0 &gpio0 15 0>,     /* GP15 */
+			<16 0 &gpio0 16 0>,     /* GP16 */
+			<17 0 &gpio0 17 0>,     /* GP17 */
+			<18 0 &gpio0 18 0>,     /* GP18 */
+			<19 0 &gpio0 19 0>,     /* GP19 */
+			<20 0 &gpio0 20 0>,     /* GP20 */
+			<21 0 &gpio0 21 0>,     /* GP21 */
+			<22 0 &gpio0 22 0>,     /* GP22 */
+			<26 0 &gpio0 26 0>,     /* GP26 */
+			<27 0 &gpio0 27 0>,     /* GP27 */
+			<28 0 &gpio0 28 0>;     /* GP28 */
+	};
+};
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_M(4)>;
+};
+
+&qmi {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&cpu1 {
+	status = "disabled";
+};
+
+&gpio0 {
+	status = "disabled";
+};

dts/examples/rpi_pico2w_debug.dts

@@ -4,8 +4,13 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+/dts-v1/;
+
+#include <rpi/pico/rp2350.dtsi>
+
 /{
 	chosen {
+        sentry,debug_stdout = <&uart0>;
 		sentry,kernelram_section = <&kernel_ram>;
 		sentry,idleram_section = <&idle_ram>;
 		sentry,kernelcode_section = <&kernel_code>;
@@ -75,6 +80,10 @@
         reg = <0x10000000 DT_SIZE_M(4)>;
 };
 
+&uart0 {
+	status = "okay";
+};
+
 &gpio0 {
     /* needs driver first */
     status = "disabled";

dts/meson.build

@@ -38,6 +38,7 @@ examples_dts_files = files(
   'examples/stm32f429i_disc1.dts',
   'examples/stm32f429i_disc1_release.dts',
   'examples/opentitan_earlgrey.dts',
+  'examples/rpi_pico2w.dts',
 )
 
 install_data(

kernel/include/bsp/drivers/meson.build

@@ -23,3 +23,4 @@ endif
 # as generated files may consume driver header
 bsp_header_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32F4', if_true: files('clk/stm32x4-pll.h'))
 bsp_header_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32L4', if_true: files('clk/stm32x4-pll.h'))
+bsp_header_set.add(when: 'CONFIG_SOC_SUBFAMILY_RP2350', if_true: files('sysinfo/sysinfo.h'))

kernel/include/bsp/drivers/sysinfo/sysinfo.h

@@ -0,0 +1,22 @@
+// SPDX-FileCopyrightText: 2026 H2Lab Development Team
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef DRV_SYSINFO_H
+#define DRV_SYSINFO_H
+
+#include <inttypes.h>
+
+#include <sentry/ktypes.h>
+
+/**
+ * @file SYSINFO hardware kernel public API.
+ */
+
+kstatus_t sysinfo_get_chip_id(uint32_t *chip_id);
+
+kstatus_t sysinfo_get_chip_revision(uint8_t *revision);
+
+/* Compatibility helper: keeps existing call sites working. */
+uint8_t sysinfo_chip_version(void);
+
+#endif /* DRV_SYSINFO_H */

kernel/include/sentry/arch/asm-cortex-m/meson.build

@@ -21,13 +21,24 @@ arch_header_set.add(when: 'CONFIG_HAS_MPU_PMSA_V7', if_true: files('mpu_pmsa_v7.
 arch_header_set.add(when: 'CONFIG_HAS_MPU_PMSA_V8', if_true: files('mpu_pmsa_v8.h'))
 
 irq_defs_in = files('irq_defs.h.in')
-# generated headers
-irq_def_h = custom_target('gen_irq_defs',
-   input: irq_defs_in,
-    output: '@BASENAME@',
-    depends: [ svd_json ],
-    command: [ jinja_cli, '-d', svd_json, '-o', '@OUTPUT@', '@INPUT@' ],
-)
+if kconfig_data.get('CONFIG_SOC_SUBFAMILY_RP2350', 0) == 1
+    # RP2350 uses a dedicated static IRQ definition list, not SVD-derived generation.
+    irq_def_h = custom_target('gen_irq_defs_rp2350',
+        input: files('rp2350/irq_defs.h.in'),
+        output: 'irq_defs.h',
+        command: [ 'cp', '@INPUT@', '@OUTPUT@' ],
+    )
+    irq_def_h_list = irq_def_h.to_list()
+else
+    # generated headers
+    irq_def_h = custom_target('gen_irq_defs',
+       input: irq_defs_in,
+        output: '@BASENAME@',
+        depends: [ svd_json ],
+        command: [ jinja_cli, '-d', svd_json, '-o', '@OUTPUT@', '@INPUT@' ],
+    )
+    irq_def_h_list = irq_def_h.to_list()
+endif
 
 layout_h = custom_target('gen_layout',
     input: layout_in,
@@ -46,7 +57,7 @@ core_h = custom_target('gen_core',
 )
 
 arch_header_set.add(
-    irq_def_h.to_list(),
+    irq_def_h_list,
     layout_h.to_list(),
     core_h.to_list(),
 )
@@ -61,6 +72,7 @@ buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32L4', if_true: files('stm32l4
 # rework this as this is weak
 buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32U5', if_true: files('stm32l4-buses.h.in'))
 buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32WB', if_true: files('stm32l4-buses.h.in'))
+buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_RP2350', if_true: files('rp2350-buses.h.in'))
 
 # here, we can add other templates for other ARM SoC famillies if needed
 buses_h_in_set_config = buses_h_in_set.apply(kconfig_data, strict: false)

kernel/include/sentry/arch/asm-cortex-m/rp2350-buses.h.in

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: Apache-2.0
+
+/*
+ * Minimal bus mapping for RP2350 clock API compatibility.
+ */
+
+#ifndef BUSES_H
+#define BUSES_H
+
+typedef enum bus_identifier {
+    BUS_GENERIC = 0,
+} bus_id_t;
+
+#define BUS_IS_VALID(bus) (true)
+
+/*@
+  logic boolean bus_is_valid(uint32_t bus) =
+    (void)bus, \true;
+*/
+
+#endif/*!BUSES_H*/

kernel/include/sentry/arch/asm-cortex-m/rp2350/irq_defs.h.in

@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: Apache-2.0
+
+/*
+ * Copyright 2026 ANSSI
+ *
+ * Hardcoded RP2350 IRQ definitions.
+ */
+
+#ifndef __RP2350_IRQ_DEFS_H
+#define __RP2350_IRQ_DEFS_H
+
+typedef void(*__irq_handler_t)(void);
+
+/**
+ * @brief IRQ num typedef that comply with cmsis header
+ */
+typedef enum IRQn
+{
+    /* core exceptions */
+    RESET_IRQ      = -15,
+    NMI_IRQ        = -14,
+    HARDFAULT_IRQ  = -13,
+    MEMMANAGE_IRQ  = -12,
+    BUSFAULT_IRQ   = -11,
+    USAGEFAULT_IRQ = -10,
+    RES7_IRQ       = -9,
+    RES8_IRQ       = -8,
+    RES9_IRQ       = -7,
+    RES10_IRQ      = -6,
+    SVC_IRQ        = -5,
+    RES12_IRQ      = -4,
+    RES13_IRQ      = -3,
+    PENDSV_IRQ     = -2,
+    SYSTICK_IRQ    = -1,
+
+    /* RP2350 SoC-defined interrupts */
+    TIMER0_IRQ_0_IRQ = 0,
+    TIMER0_IRQ_1_IRQ = 1,
+    TIMER0_IRQ_2_IRQ = 2,
+    TIMER0_IRQ_3_IRQ = 3,
+    TIMER1_IRQ_0_IRQ = 4,
+    TIMER1_IRQ_1_IRQ = 5,
+    TIMER1_IRQ_2_IRQ = 6,
+    TIMER1_IRQ_3_IRQ = 7,
+    PWM_IRQ_WRAP_0_IRQ = 8,
+    PWM_IRQ_WRAP_1_IRQ = 9,
+    DMA_IRQ_0_IRQ = 10,
+    DMA_IRQ_1_IRQ = 11,
+    DMA_IRQ_2_IRQ = 12,
+    DMA_IRQ_3_IRQ = 13,
+    USBCTRL_IRQ_IRQ = 14,
+    PIO0_IRQ_0_IRQ = 15,
+    PIO0_IRQ_1_IRQ = 16,
+    PIO1_IRQ_0_IRQ = 17,
+    PIO1_IRQ_1_IRQ = 18,
+    PIO2_IRQ_0_IRQ = 19,
+    PIO2_IRQ_1_IRQ = 20,
+    IO_IRQ_BANK0_IRQ = 21,
+    IO_IRQ_BANK0_NS_IRQ = 22,
+    IO_IRQ_QSPI_IRQ = 23,
+    IO_IRQ_QSPI_NS_IRQ = 24,
+    SIO_IRQ_FIFO_IRQ = 25,
+    SIO_IRQ_BELL_IRQ = 26,
+    SIO_IRQ_FIFO_NS_IRQ = 27,
+    SIO_IRQ_BELL_NS_IRQ = 28,
+    SIO_IRQ_MTIMECMP_IRQ = 29,
+    CLOCKS_IRQ_IRQ = 30,
+    SPI0_IRQ_IRQ = 31,
+    SPI1_IRQ_IRQ = 32,
+    UART0_IRQ_IRQ = 33,
+    UART1_IRQ_IRQ = 34,
+    ADC_IRQ_FIFO_IRQ = 35,
+    I2C0_IRQ_IRQ = 36,
+    I2C1_IRQ_IRQ = 37,
+    OTP_IRQ_IRQ = 38,
+    TRNG_IRQ_IRQ = 39,
+    PLL_SYS_IRQ_IRQ = 42,
+    PLL_USB_IRQ_IRQ = 43,
+    POWMAN_IRQ_POW_IRQ = 44,
+    POWMAN_IRQ_TIMER_IRQ = 45,
+} IRQn_Type;
+
+/** @brief total number of connected IRQ line in current SoC */
+#define __NVIC_VECTOR_LEN 46
+/** @brief bitfield size of NVIC interrupt lines priority */
+#define __NVIC_PRIO_BITS 4
+
+#endif /* __RP2350_IRQ_DEFS_H */

kernel/src/arch/asm-cortex-m/Kconfig

@@ -87,6 +87,13 @@ config SOC_FAMILY_STM32
 	bool
 	select LITTLE_ENDIAN
 
+config SOC_FAMILY_RP2
+	bool
+	select LITTLE_ENDIAN
+	select HAS_FPU
+	select HAS_FPU_VFPV4
+	select HAS_MPU_PMSA_V8
+
 config SOC_SUBFAMILY_STM32F4
 	bool
 	select ARCH_ARM_CORTEX_M4
@@ -177,6 +184,13 @@ config SOC_SUBFAMILY_STM32U5F_Gx
 	bool
 	select SOC_SUBFAMILY_STM32U5
 
+config SOC_SUBFAMILY_RP2350
+	bool
+	select ARCH_ARM_CORTEX_M33
+	select SOC_FAMILY_RP2
+	help
+	  RP2350 family is based on Cortex-M33 with SMP support.
+
 config ARCH_ARM_CORTEX_NAME
 	string
 	default "m3" if ARCH_ARM_CORTEX_M3
@@ -205,6 +219,7 @@ config ARCH_SOCNAME
 	default "STM32U5A9" if ARCH_MCU_STM32U5A9
 	default "STM32U5FX" if ARCH_MCU_STM32U5FX
 	default "STM32U5GX" if ARCH_MCU_STM32U5GX
+	default "RP2350" if ARCH_MCU_RP2350
 
 # User-accessible selectors
 
@@ -252,6 +267,10 @@ config ARCH_MCU_STM32U5A9
 	bool "STM32U5A9"
 	select SOC_SUBFAMILY_STM32U59_Ax
 
+config ARCH_MCU_RP2350
+	bool "RP2350"
+	select SOC_SUBFAMILY_RP2350
+
 endchoice
 
 if HAS_FPU
@@ -298,6 +317,7 @@ config FPU_ABI_CFLAGS
 	default "-mfloat-abi=softfp" if FPU_SOFTFP_ABI
 	default "-mfloat-abi=hard" if FPU_HARDFP_ABI
 
+
 config FPU_CFLAGS
 	string
 	depends on !FPU_SOFT_ABI
@@ -318,4 +338,4 @@ config RUSTC_TARGET
 	default "thumbv8m.main-none-eabi" if ARCH_ARM_ARMV8MML && !FPU_HARDFP_ABI
 	default "thumbv8m.main-none-eabihf" if ARCH_ARM_ARMV8MML && FPU_HARDFP_ABI
 
-endmenu
+endmenu