Add ADSY1100 and other minor fixes

adidt/__init__.py

@@ -9,3 +9,4 @@
 from adidt.boards.ad9081_fmc import ad9081_fmc
 from adidt.boards.adrv9009_zu11eg import adrv9009_zu11eg
 from adidt.boards.adrv9009_pcbz import adrv9009_pcbz
+from adidt.boards.adsy1100 import adsy1100_vu11p

adidt/boards/__init__.py

@@ -1,2 +1,5 @@
 from adidt.boards.daq2 import daq2
 from adidt.boards.ad9081_fmc import ad9081_fmc
+from adidt.boards.adrv9009_zu11eg import adrv9009_zu11eg
+from adidt.boards.adrv9009_pcbz import adrv9009_pcbz
+from adidt.boards.adsy1100 import adsy1100_vu11p

adidt/boards/adsy1100.py

@@ -0,0 +1,77 @@
+from .layout import layout
+import numpy as np
+
+
+class adsy1100_vu11p(layout):
+    """ADSY1100 VU11P board layout map for clocks and DSP"""
+
+    clock = "LTC6952"
+
+    adc = "ad9081_rx"
+    dac = "ad9081_tx"
+
+    template_filename = "adsy1100_vu11p.tmpl"
+    output_filename = "adsy1100_vu11p.dts"
+
+    def make_ints(self, cfg, keys):
+        """Convert keys in a dict to integers.
+
+        Args:
+            cfg (dict): Configuration.
+            keys (list): Keys to convert.
+
+        Returns:
+            dict: Configuration with keys converted to integers.
+        """
+        for key in keys:
+            if isinstance(cfg[key], float) and cfg[key].is_integer():
+                cfg[key] = int(cfg[key])
+        return cfg
+
+    def map_clocks_to_board_layout(self, cfg):
+        """Map JIF configuration to board clock connection layout.
+
+        Args:
+            cfg (dict): JIF configuration.
+
+        Returns:
+            dict: Board clock connection layout.
+        """
+        # Fix ups
+        for key in ["VCO", "vcxo"]:
+            cfg["clock"][key] = int(np.ceil(cfg["clock"][key]))
+
+        map = {}
+        clk = cfg["clock"]["output_clocks"]
+
+        # Common
+        map["sysref_divider"] = {
+            "source_port": 3,
+            "divider": clk["AD9084_RX_sysref"]["divider"],
+        }
+
+        # AD9084 ext PLL
+        map["converter_clock_rate"] = np.ceil(cfg["clock_ext_pll_adf4382"]["rf_out_frequency"])
+        map["converter_clock_rate"] = int(map["converter_clock_rate"])
+
+        # FPGA side
+        map["ref_clk_divider"] = {
+            "source_port": 3,
+            "divider": clk["adsy1100_AD9084_RX_ref_clk"]["divider"],
+        }
+
+        map["core_clk_divider"] = {
+            "source_port": 0,
+            "divider": clk["adsy1100_AD9084_RX_device_clk"]["divider"],
+        }
+
+        ccfg = {"map": map, "clock": cfg["clock"]}
+
+        fpga = {}
+        fpga['fpga'] = cfg["fpga_AD9084_RX"]
+        if fpga['fpga']['sys_clk_select'] == 'XCVR_QPLL0':
+            fpga['fpga']['sys_clk_select'] = 'XCVR_QPLL'
+        # fpga['fpga_dac'] = cfg["fpga_dac"]
+
+
+        return ccfg, fpga

adidt/boards/layout.py

@@ -1,4 +1,4 @@
-from jinja2 import Environment, FileSystemLoader
+from jinja2 import Environment, FileSystemLoader, StrictUndefined
 import os
 
 
@@ -33,7 +33,7 @@ def gen_dt(self, **kwargs):
         loc = os.path.dirname(__file__)
         loc = os.path.join(loc, "..", "templates")
         file_loader = FileSystemLoader(loc)
-        env = Environment(loader=file_loader)
+        env = Environment(loader=file_loader, undefined=StrictUndefined)
 
         loc = os.path.join(self.template_filename)
         template = env.get_template(loc)