Tfcollins/adrv9009 parser

.codespell-whitelist

@@ -0,0 +1,6 @@
+AFE
+afe
+SOM
+som
+sinc
+byteorder

.github/workflows/test.yml

@@ -13,5 +13,6 @@ jobs:
       with:
         python-version: ${{ matrix.python-version }}
         architecture: x64
+    - run: sudo apt install -y gcc-aarch64-linux-gnu make bc u-boot-tools flex bison libssl-dev tar kmod
     - run: pip install -r requirements/requirements_dev.txt
     - run: pytest -vs

.pre-commit-config.yaml

@@ -0,0 +1,36 @@
+repos:
+      #-   repo: https://github.com/codespell-project/codespell
+      #    rev: v1.15.0
+      #    hooks:
+      #    -   id: codespell
+      #        args: [--ignore-words=.codespell-whitelist,--exclude-file=examples/cn0549/ml_fan_example.ipynb]
+-   repo: https://github.com/pre-commit/mirrors-isort
+    rev: v4.3.20
+    hooks:
+    -   id: isort
+      #-   repo: https://github.com/pre-commit/mirrors-mypy
+      #    rev: v0.720
+      #    hooks:
+      #    -   id: mypy
+      #        args: [--no-strict-optional, --ignore-missing-imports]
+-   repo: https://github.com/pre-commit/pre-commit-hooks
+    rev: v2.3.0
+    hooks:
+    -   id: check-yaml
+    -   id: end-of-file-fixer
+    -   id: trailing-whitespace
+    -   id: check-merge-conflict
+    -   id: debug-statements
+    -   id: check-docstring-first
+    -   id: flake8
+-   repo: https://github.com/psf/black
+    rev: 19.10b0
+    hooks:
+    - id: black
+      language_version: python3
+      additional_dependencies: ['click==8.0.4']
+-   repo: https://github.com/asottile/blacken-docs
+    rev: v1.12.0
+    hooks:
+    -   id: blacken-docs
+        additional_dependencies: [black==19.10b0]

adidt/__init__.py

@@ -1,8 +1,10 @@
-from adidt.dt import dt
-from adidt.clock import clock
-from adidt.parts.hmc7044 import hmc7044_dt
+from adidt.boards.ad9081_fmc import ad9081_fmc
+from adidt.boards.adrv9009_zu11eg import adrv9009_zu11eg
+from adidt.boards.daq2 import daq2
 from adidt.parts.ad9523_1 import ad9523_1_dt
 from adidt.parts.ad9545 import ad9545_dt
+from adidt.parts.adrv9009 import adrv9009_dt
+from adidt.parts.hmc7044 import hmc7044_dt
 
-from adidt.boards.daq2 import daq2
-from adidt.boards.ad9081_fmc import ad9081_fmc
+from .clock import clock
+from .dt import dt

adidt/boards/__init__.py

@@ -1,2 +1,2 @@
-from adidt.boards.daq2 import daq2
 from adidt.boards.ad9081_fmc import ad9081_fmc
+from adidt.boards.daq2 import daq2

adidt/boards/ad9081_fmc.py

@@ -1,6 +1,7 @@
-from .layout import layout
 import numpy as np
 
+from .layout import layout
+
 
 class ad9081_fmc(layout):
     """AD9081 FMC board layout map for clocks and DSP"""
@@ -119,8 +120,8 @@ def map_clocks_to_board_layout(self, cfg):
         ccfg = {"map": map, "clock": cfg["clock"]}
 
         fpga = {}
-        fpga['fpga_adc'] = cfg["fpga_adc"]
-        fpga['fpga_dac'] = cfg["fpga_dac"]
+        fpga["fpga_adc"] = cfg["fpga_adc"]
+        fpga["fpga_dac"] = cfg["fpga_dac"]
 
         # Check all clocks are mapped
         # FIXME

adidt/boards/adrv9009_zu11eg.py

@@ -0,0 +1,202 @@
+import os
+
+import numpy as np
+
+from ..parts.adrv9009 import parse_profile
+from .layout import layout
+
+
+def coefs_to_long_string(coefs):
+    """Convert coefficient array to string.
+
+    Args:
+        coefs (list): Coefficients.
+
+    Returns:
+        str: Coefficients as a string.
+    """
+    result = ""
+    for coef in coefs.split("\n"):
+        coef = coef.replace(" ", "")
+        result += f"({coef}) "
+    return result[:-1]
+
+
+class adrv9009_zu11eg(layout):
+    """ADRV9009-ZU11EG SOM board layout map for clocks and DSP"""
+
+    clock = "HMC7044"
+
+    adc = "adrv9009_rx"
+    dac = "adrv9009_tx"
+
+    template_filename = "adrv9009_zu11eg.dts"
+    output_filename = "adrv9009_zu11eg_out.dts"
+
+    profile = None
+
+    def gen_dt_preprocess(self):
+        """Preprocess profile for transceiver.
+
+        Args:
+            profile (dict): Profile.
+
+        Returns:
+            dict: Preprocessed profile.
+        """
+        if self.profile is None:
+            raise Exception("Profile not loaded")
+        rx = self.profile["rx"]
+        tx = self.profile["tx"]
+        orx = self.profile["obsRx"]
+        lpbk = self.profile["lpbk"]
+        clocks = self.profile["clocks"]
+
+        rx["rxAdcProfile"]["coefs"] = coefs_to_long_string(rx["rxAdcProfile"]["#text"])
+        rx["filter"]["coefs"] = coefs_to_long_string(rx["filter"]["#text"])
+
+        orx["filter"]["coefs"] = coefs_to_long_string(orx["filter"]["#text"])
+        orx["orxBandPassAdcProfile"]["coefs"] = coefs_to_long_string(
+            orx["orxBandPassAdcProfile"]["#text"]
+        )
+        orx["orxLowPassAdcProfile"]["coefs"] = coefs_to_long_string(
+            orx["orxLowPassAdcProfile"]["#text"]
+        )
+
+        tx["filter"]["coefs"] = coefs_to_long_string(tx["filter"]["#text"])
+        lpbk["lpbkAdcProfile"]["coefs"] = coefs_to_long_string(
+            lpbk["lpbkAdcProfile"]["#text"]
+        )
+
+        return {"rx": rx, "tx": tx, "orx": orx, "lpbk": lpbk, "clocks": clocks}
+
+    def make_ints(self, cfg, keys):
+        """Convert keys in a dict to integers.
+
+        Args:
+            cfg (dict): Configuration.
+            keys (list): Keys to convert.
+
+        Returns:
+            dict: Configuration with keys converted to integers.
+        """
+        for key in keys:
+            if isinstance(cfg[key], float) and cfg[key].is_integer():
+                cfg[key] = int(cfg[key])
+        return cfg
+
+    def map_jesd_structs(self, cfg):
+        """Map JIF configuration to integer structs.
+
+        Args:
+            cfg (dict): JIF configuration.
+
+        Returns:
+            dict: ADC JESD structs.
+            dict: DAC JESD structs.
+        """
+        adc = cfg["converter"]
+        adc["jesd"] = cfg["jesd_adc"]
+        adc["jesd"]["jesd_class_int"] = self.map_jesd_subclass(
+            adc["jesd"]["jesd_class"]
+        )
+        dac = cfg["converter"].copy()
+        dac["jesd"] = cfg["jesd_dac"]
+        dac["jesd"]["jesd_class_int"] = self.map_jesd_subclass(
+            dac["jesd"]["jesd_class"]
+        )
+
+        adc["jesd"] = self.make_ints(adc["jesd"], ["converter_clock", "sample_clock"])
+        dac["jesd"] = self.make_ints(dac["jesd"], ["converter_clock", "sample_clock"])
+
+        adc["datapath"] = cfg["datapath_adc"]
+        dac["datapath"] = cfg["datapath_dac"]
+
+        return adc, dac
+
+    def map_clocks_to_board_layout(self, cfg):
+        """Map JIF configuration to board clock connection layout.
+
+        Args:
+            cfg (dict): JIF configuration.
+
+        Returns:
+            dict: Board clock connection layout.
+        """
+        # Fix ups
+        for key in ["vco", "vcxo"]:
+            if isinstance(cfg["clock"][key], float) and cfg["clock"][key].is_integer():
+                cfg["clock"][key] = int(cfg["clock"][key])
+
+        map = {}
+        clk = cfg["clock"]["output_clocks"]
+
+        # Common
+        map["DEV_REFCLK"] = {
+            "source_port": 2,
+            "divider": clk["AD9081_ref_clk"]["divider"],
+        }
+        map["DEV_SYSREF"] = {
+            "source_port": 3,
+            "divider": np.max(
+                [clk["adc_sysref"]["divider"], clk["dac_sysref"]["divider"]]
+            ),
+        }
+        map["FPGA_SYSREF"] = {
+            "source_port": 13,
+            "divider": np.max(
+                [clk["adc_fpga_ref_clk"]["divider"], clk["dac_fpga_ref_clk"]["divider"]]
+            ),
+        }
+
+        # RX side
+        map["CORE_CLK_RX"] = {
+            "source_port": 0,
+            "divider": clk["adc_fpga_ref_clk"]["divider"],
+        }
+        map["CORE_CLK_RX_ALT"] = {
+            "source_port": 10,
+            "divider": clk["adc_fpga_ref_clk"]["divider"] * 2,
+        }
+        map["FPGA_REFCLK1"] = {
+            "source_port": 8,
+            "divider": clk["adc_fpga_ref_clk"]["divider"],
+        }
+
+        # Tx side
+        map["CORE_CLK_TX"] = {
+            "source_port": 6,
+            "divider": clk["dac_fpga_ref_clk"]["divider"],
+        }
+        map["FPGA_REFCLK2"] = {
+            "source_port": 12,
+            "divider": clk["dac_fpga_ref_clk"]["divider"],
+        }
+
+        ccfg = {"map": map, "clock": cfg["clock"]}
+
+        fpga = {}
+        fpga["fpga_adc"] = cfg["fpga_adc"]
+        fpga["fpga_dac"] = cfg["fpga_dac"]
+
+        # Check all clocks are mapped
+        # FIXME
+
+        # Check no source_port is mapped to more than one clock
+        # FIXME
+        adc, dac = self.map_jesd_structs(cfg)
+
+        return ccfg, adc, dac, fpga
+
+    def parse_profile(self, filename):
+        """Parse a profile file.
+
+        Args:
+            filename (str): Profile file name.
+
+        Returns:
+            dict: Profile configuration.
+        """
+        if not os.path.exists(filename):
+            raise Exception(f"Profile file not found: {filename}")
+        self.profile = parse_profile(filename)

adidt/boards/daq2.py

@@ -1,4 +1,3 @@
-
 from .layout import layout
 
 

adidt/boards/layout.py

@@ -1,6 +1,7 @@
-from jinja2 import Environment, FileSystemLoader
 import os
 
+from jinja2 import Environment, FileSystemLoader
+
 
 class layout:
     """Common Layout Class for DT generation templates."""
@@ -10,6 +11,9 @@ class layout:
     template_filename = None
     output_filename = None
 
+    # def gen_dt_preprocess(self, **kwargs):
+    #     return kwargs
+
     def gen_dt(self, **kwargs):
         """Generate the DT file from configuration structs.
 
@@ -34,6 +38,8 @@ def gen_dt(self, **kwargs):
 
         loc = os.path.join(self.template_filename)
         template = env.get_template(loc)
+
+        kwargs = self.gen_dt_preprocess(**kwargs)
         output = template.render(**kwargs)
 
         with open(self.output_filename, "w") as f:

adidt/cli/helpers.py

@@ -1,6 +1,6 @@
+from rich import box
 from rich.console import Console
 from rich.table import Column, Table
-from rich import box
 from rich.text import Text
 
 console = Console()