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library/axi_ad408x: Add configurable NUM_LANES parameter for single-lane support #2043

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Merged
robert-bocos merged 2 commits into from
Apr 22, 2026
+28 −9
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library/axi_ad408x: Add configurable NUM_LANES parameter for single-lane support #2043

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library/axi_ad408x: Add configurable NUM_LANES parameter for single-l…
robert-bocos Mar 30, 2026
64c4803
library/axi_ad408x: Update copyright year range to include 2026
robert-bocos Apr 1, 2026
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31 changes: 24 additions & 7 deletions library/axi_ad408x/ad408x_phy.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2022-2026 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL(Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -237,8 +237,15 @@ module ad408x_phy #(
end
endgenerate

assign serdes_in_p = {data_b_in_p, data_a_in_p};
assign serdes_in_n = {data_b_in_n, data_a_in_n};
generate
if (NUM_LANES == 2) begin
assign serdes_in_p = {data_b_in_p, data_a_in_p};
assign serdes_in_n = {data_b_in_n, data_a_in_n};
end else begin
assign serdes_in_p = data_a_in_p;
assign serdes_in_n = data_a_in_n;
end
endgenerate

// Min 2 div_clk cycles once div_clk is running after deassertion of sync
// Control externally the reset of serdes for precise timing
Expand Down Expand Up @@ -285,10 +292,20 @@ module ad408x_phy #(
.delay_rst(delay_rst),
.delay_locked(delay_locked));

assign {serdes_data_1[0],serdes_data_0[0]} = data_s0; // f-e latest bit received
assign {serdes_data_1[1],serdes_data_0[1]} = data_s1; // r-e
assign {serdes_data_1[2],serdes_data_0[2]} = data_s2; // f-e
assign {serdes_data_1[3],serdes_data_0[3]} = data_s3; // r-e oldest bit received
generate
if (NUM_LANES == 2) begin
assign {serdes_data_1[0],serdes_data_0[0]} = data_s0; // f-e latest bit received
assign {serdes_data_1[1],serdes_data_0[1]} = data_s1; // r-e
assign {serdes_data_1[2],serdes_data_0[2]} = data_s2; // f-e
assign {serdes_data_1[3],serdes_data_0[3]} = data_s3; // r-e oldest bit received
end else begin
assign serdes_data_0[0] = data_s0;
assign serdes_data_0[1] = data_s1;
assign serdes_data_0[2] = data_s2;
assign serdes_data_0[3] = data_s3;
assign serdes_data_1 = 4'b0;
end
endgenerate

// Assert serdes valid after 2 clock cycles is pulled out of reset

Expand Down
6 changes: 4 additions & 2 deletions library/axi_ad408x/axi_ad408x.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2022-2026 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL(Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -38,6 +38,7 @@
module axi_ad408x #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter NUM_LANES = 2,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter ADC_N_BITS = 20
) (
Expand Down Expand Up @@ -96,7 +97,7 @@ module axi_ad408x #(
input [ 2:0] s_axi_arprot
);

localparam DELAY_CTRL_NUM_LANES = 2;
localparam DELAY_CTRL_NUM_LANES = NUM_LANES;
localparam DELAY_CTRL_DRP_WIDTH = 5;
localparam ADC_DATA_WIDTH = ((ADC_N_BITS > 16)? 32 : 16);

Expand Down Expand Up @@ -276,6 +277,7 @@ module axi_ad408x #(

ad408x_phy #(
.FPGA_TECHNOLOGY(FPGA_TECHNOLOGY),
.NUM_LANES(NUM_LANES),
.IO_DELAY_GROUP(IO_DELAY_GROUP),
.IODELAY_CTRL(1),
.ADC_N_BITS(ADC_N_BITS),
Expand Down
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