library/util_axis_fifo_asym: Insert reg slice#2031
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This library had timing issues when RATIO is high. To improve that, it was inserted a register slice into the library that is enabled only when required. To avoid any latency on the current projects, SRC_REG_SLICE_EN is disabled by default. Note: register slice definition is inside the DMA. I chose not to move the IP to a common folder to avoid another PR. Future solution need to consider moving this register slice library to common folder in the libraries. Signed-off-by: Carlos Souza <carlos.souza@analog.com>
Insert information about the SRC_REG_SLICE_EN, which enables the register slice into the FIFO ASYM. Signed-off-by: Carlos Souza <carlos.souza@analog.com>
caosjr
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IuliaCMoldovan,
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sarpadi
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This library had timing issues when RATIO is high. To improve that, it was inserted a register slice into the library that is enabled only when required.
To avoid any latency on the current projects, SRC_REG_SLICE_EN is disabled by default.
Note: register slice definition is inside the DMA. I chose not to move the IP to a common folder to avoid another PR. Future solution need to consider moving this register slice library to common folder in the libraries.
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