library: Add axi_adf4030 IP for AION bsync and triggers synchronization

[FilipG24]

PR Description

axi_adf4030 is an AXI4-Lite IP core for interfacing with the ADF4030 chip (used with latest Apollo based projects for Multi-Chip Sync).

Key capabilities:

• Bidirectional BSYNC interface: Can receive external or generate internal BSYNC signal via differential I/O (IOBUFDS_DCIEN)
• Multi-channel trigger system: Up to 8 trigger channels with per-channel phase adjustment, synchronized to BSYNC events
• Multiple trigger modes: External, manual (software), and debug trigger sources
• BSYNC calibration: Auto-calibrates ratio/timing with alignment error detection
• Async Trigger pulse stretcher: used for generating a trigger pulse without sampling the BSYNC edge
• Xilinx device support: UltraScale, Versal AI Core, Versal Premium

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)
• Documentation

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones