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CPACK/UPACK: Add pipeline support#2024

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FilipG24 wants to merge 3 commits intomainfrom
util_pack_pipeline
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CPACK/UPACK: Add pipeline support#2024
FilipG24 wants to merge 3 commits intomainfrom
util_pack_pipeline

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@FilipG24 FilipG24 commented Mar 9, 2026

PR Description

High-speed JESD204B/C designs with many converters (high M) or many samples per converter (high S) face timing challenges in the cpack/upack routing networks. The long combinational paths through multiple MUX stages can become critical paths, limiting achievable clock frequencies.

This PR adds configurable pipelining support to util_cpack2 and util_upack2 cores to improve timing closure for high-speed JESD designs with large converter counts or high sample rates.

Key Features:

  • New PIPELINE_STAGES parameter to control pipeline depth (possible values are: 0 = no pipeline, 1 = pipeline every 2 stages, 2 = pipeline every stage)
  • Clock enabled pipeline stages to maintain proper data alignment
  • Backwards compatible, default behavior unchanged (with PIPELINE_STAGES=0)

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

Custom pipelining using PIPELINE_STAGES parameter: 0 = no pipeline, 1 = pipeline every 2 stages, 2 = pipeline every stage

Signed-off-by: Filip Gherman <filip.gherman@analog.com>
@FilipG24 FilipG24 requested a review from AndreiGrozav as a code owner March 9, 2026 14:22
@FilipG24 FilipG24 force-pushed the util_pack_pipeline branch 3 times, most recently from 0f01a4c to 1c01c17 Compare March 9, 2026 15:32
FilipG24 added 2 commits March 9, 2026 17:35
Add PIPELINE_OFFSET parameter to account for cumulative pipeline delay when multiple pack_networks are cascaded.
Previously, control signals for later networks were not delayed to match the data
pipeline latency accumulated from earlier networks, causing data corruption
with larger channel configurations(in case of odd or non-power of two channel enables).

Signed-off-by: Filip Gherman <filip.gherman@analog.com>
Add testbenches for 8, 32, 64 channel configurations to verify
util_cpack2 behavior across various JESD204 use cases:

 -cpack_8ch_tb (M=8,  S=4)
 -cpack_32ch_tb(M=32, S=1)
 -cpack_64ch_tb(M=64, S=1)

Signed-off-by: Filip Gherman <filip.gherman@analog.com>
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