projects/admx100x_evb: Add RX part to the project

docs/projects/admx100x_evb/index.rst

@@ -18,8 +18,16 @@ systems. The integrated DPD algorithm minimizes distortion typically introduced
 by DAC and amplifier stages, enabling the generation of extremely clean test
 signals for precision measurement applications. The ADMX1002 focuses solely on
 high-fidelity signal generation, providing a streamlined solution for setups
-where local signal acquisition is not required. Note that in the current HDL
-release, only the TX path is implemented and supported.
+where local signal acquisition is not required.
+
+The HDL reference design implements both the TX signal generation path and the
+RX acquisition path. The RX path uses an :adi:`ADAQ7768-1` precision ADC,
+enabling simultaneous signal generation and capture on the ADMX1001.
+
+This project has a :ref:`SPI Engine <spi_engine>` instance to control and
+acquire data from the :adi:`ADAQ7768-1` 24-bit precision ADC. This instance
+provides support for capturing continuous samples at the maximum sample rate
+of 256 kSPS.
 
 Supported boards
 -------------------------------------------------------------------------------
@@ -31,6 +39,7 @@ Supported devices
 -------------------------------------------------------------------------------
 
 - :adi:`AD5683R`
+- :adi:`ADAQ7768-1`
 
 Supported carriers
 -------------------------------------------------------------------------------
@@ -52,6 +61,12 @@ Supported carriers
 Block design
 -------------------------------------------------------------------------------
 
+The reference design uses the :ref:`SPI Engine Framework <spi_engine>` to
+interface with the :adi:`ADAQ7768-1` precision ADC on the RX acquisition path.
+The :ref:`SPI Engine Offload module <spi_engine offload>` is used to capture
+continuous samples at the maximum sample rate of 256 kSPS, triggered by the
+DRDY (data ready) signal of the :adi:`ADAQ7768-1`.
+
 .. warning::
 
     The VADJ for the Zedboard must be set to 3.3V.
@@ -61,7 +76,7 @@ Block diagram
 
 The data path and clock domains are depicted in the below diagram:
 
-.. image:: admx100x-evb.svg
+.. image:: admx100x_evb.svg
    :width: 800
    :align: center
    :alt: ADMX100X/ZedBoard block diagram
@@ -79,16 +94,24 @@ SPI connections
      - CS
    * - PS
      - SPI 0
-     - CS_DAC
+     - CS_FPGA
      - 0
    * - PS
      - SPI 0
-     - CS_FPGA
+     - CS_DAC
+     - 1
+   * - PL
+     - axi_spi_engine
+     - ADAQ7768-1
      - 0
 
 GPIOs
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+The Software GPIO number is calculated as follows:
+
+- Zynq-7000: if PS7 is used, then offset is 54
+
 .. list-table::
    :widths: 25 25 25 25
    :header-rows: 2
@@ -101,43 +124,81 @@ GPIOs
      - (from FPGA view)
      -
      - Zynq-7000
-   * - ADMX100X_SYNC_MODE
-     - OUT
-     - 34
-     - 88
-   * - ADMX100X_EN
+   * - ACQ_DRDY
+     - IN
+     - 43
+     - 97
+   * - ACQ_RESET
      - OUT
-     - 35
-     - 89
-   * - ADMX100X_CAL
+     - 42
+     - 96
+   * - ACQ_SYNQ_IN_FMC
      - OUT
-     - 38
-     - 92
+     - 41
+     - 95
    * - ADMX100X_TRIG
-     - OUT
+     - IN
      - 40
      - 94
    * - ADMX100X_DAC_LDAC
      - OUT
      - 39
      - 93
-   * - ADMX100X_RESET
+   * - ADMX100X_CAL
+     - IN
+     - 38
+     - 92
+   * - ADMX100X_VALID
      - OUT
-     - 33
-     - 87
+     - 37
+     - 91
    * - ADMX100X_READY
-     - IN
+     - OUT
      - 36
      - 90
-   * - ADMX100X_VALID
+   * - ADMX100X_EN
+     - OUT
+     - 35
+     - 89
+   * - ADMX100X_SYNC_MODE
      - IN
-     - 37
-     - 91
+     - 34
+     - 88
+   * - ADMX100X_RESET
+     - OUT
+     - 33
+     - 87
    * - ADMX100X_OT
-     - IN
+     - OUT
      - 32
      - 86
 
+CPU/Memory interconnects addresses
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The addresses are dependent on the architecture of the FPGA, having an offset
+added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`).
+
+========================  ===========
+Instance                  Zynq
+========================  ===========
+spi_adaq77681_axi_regmap  0x44A0_0000
+axi_adaq77681_dma         0x44A3_0000
+spi_clkgen                0x44A7_0000
+========================  ===========
+
+Interrupts
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Below are the Programmable Logic interrupts used in this project.
+
+=================== === ========== ===========
+Instance name       HDL Linux Zynq Actual Zynq
+=================== === ========== ===========
+axi_adaq77681_dma   13  57         89
+spi_adaq77681       12  56         88
+=================== === ========== ===========
+
 Building the HDL project
 -------------------------------------------------------------------------------
 
@@ -169,6 +230,7 @@ Hardware related
 - Product datasheets:
 
   - :adi:`AD5683R`
+  - :adi:`ADAQ7768-1`
 
 HDL related
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -188,6 +250,18 @@ HDL related
    * - AXI_DMAC
      - :git-hdl:`library/axi_dmac`
      - :ref:`axi_dmac`
+   * - AXI_SPI_ENGINE
+     - :git-hdl:`library/spi_engine/axi_spi_engine`
+     - :ref:`spi_engine axi`
+   * - SPI_ENGINE_EXECUTION
+     - :git-hdl:`library/spi_engine/spi_engine_execution`
+     - :ref:`spi_engine execution`
+   * - SPI_ENGINE_INTERCONNECT
+     - :git-hdl:`library/spi_engine/spi_engine_interconnect`
+     - :ref:`spi_engine interconnect`
+   * - SPI_ENGINE_OFFLOAD
+     - :git-hdl:`library/spi_engine/spi_engine_offload`
+     - :ref:`spi_engine offload`
    * - AXI_HDMI_TX
      - :git-hdl:`library/axi_hdmi_tx`
      - :ref:`axi_hdmi_tx`
@@ -207,6 +281,8 @@ HDL related
      - :git-hdl:`library/util_i2c_mixer`
      - ---
 
+- :ref:`SPI Engine Framework documentation <spi_engine>`
+
 .. include:: ../common/more_information.rst
 
 .. include:: ../common/support.rst

projects/admx100x_evb/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2025 Analog Devices, Inc.
+## Copyright (c) 2018 - 2026 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################

projects/admx100x_evb/common/admx100x_evb_bd.tcl

@@ -0,0 +1,84 @@
+###############################################################################
+## Copyright (C) 2026 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi
+
+create_bd_port -dir I adc_data_ready
+create_bd_port -dir O mclk_clk
+
+# create a SPI Engine architecture for ADC
+
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+set data_width    32
+set async_spi_clk 1
+set num_cs        1
+set num_sdi       1
+set num_sdo       1
+set sdi_delay     1
+set echo_sclk     0
+
+set hier_spi_engine spi_adaq77681
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+
+ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_offload CONFIG.ASYNC_TRIG 1
+
+ad_ip_instance axi_clkgen spi_clkgen
+ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
+ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
+ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
+
+ad_ip_instance clk_wiz mclk_clk_wiz
+ad_ip_parameter mclk_clk_wiz CONFIG.PRIMITIVE MMCM
+ad_ip_parameter mclk_clk_wiz CONFIG.RESET_TYPE ACTIVE_LOW
+ad_ip_parameter mclk_clk_wiz CONFIG.USE_LOCKED false
+ad_ip_parameter mclk_clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 16.384
+ad_ip_parameter mclk_clk_wiz CONFIG.PRIM_SOURCE No_buffer
+
+# dma for the ADC
+
+ad_ip_instance axi_dmac axi_adaq77681_dma
+ad_ip_parameter axi_adaq77681_dma CONFIG.DMA_TYPE_SRC 1
+ad_ip_parameter axi_adaq77681_dma CONFIG.DMA_TYPE_DEST 0
+ad_ip_parameter axi_adaq77681_dma CONFIG.CYCLIC 0
+ad_ip_parameter axi_adaq77681_dma CONFIG.SYNC_TRANSFER_START 0
+ad_ip_parameter axi_adaq77681_dma CONFIG.AXI_SLICE_SRC 0
+ad_ip_parameter axi_adaq77681_dma CONFIG.AXI_SLICE_DEST 1
+ad_ip_parameter axi_adaq77681_dma CONFIG.DMA_2D_TRANSFER 0
+ad_ip_parameter axi_adaq77681_dma CONFIG.DMA_DATA_WIDTH_SRC 32
+ad_ip_parameter axi_adaq77681_dma CONFIG.DMA_DATA_WIDTH_DEST 64
+
+ad_connect $sys_cpu_clk spi_clkgen/clk
+ad_connect spi_clk spi_clkgen/clk_0
+ad_connect adc_data_ready $hier_spi_engine/trigger
+ad_connect axi_adaq77681_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
+ad_connect $hier_spi_engine/m_spi adc_spi
+ad_connect $sys_cpu_clk $hier_spi_engine/clk
+ad_connect spi_clk $hier_spi_engine/spi_clk
+ad_connect spi_clk axi_adaq77681_dma/s_axis_aclk
+ad_connect sys_cpu_resetn $hier_spi_engine/resetn
+ad_connect sys_cpu_resetn axi_adaq77681_dma/m_dest_axi_aresetn
+
+ad_connect sys_cpu_clk mclk_clk_wiz/clk_in1
+ad_connect sys_cpu_resetn mclk_clk_wiz/resetn
+
+ad_connect mclk_clk mclk_clk_wiz/clk_out1
+
+# AXI address definitions
+
+ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
+ad_cpu_interconnect 0x44a30000 axi_adaq77681_dma
+ad_cpu_interconnect 0x44a70000 spi_clkgen
+
+# interrupts
+
+ad_cpu_interrupt "ps-13" "mb-13" axi_adaq77681_dma/irq
+ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
+
+# memory interconnects
+
+ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
+ad_mem_hp2_interconnect sys_cpu_clk axi_adaq77681_dma/m_dest_axi

projects/admx100x_evb/zed/Makefile

@@ -1,15 +1,17 @@
 ####################################################################################
-## Copyright (c) 2018 - 2025 Analog Devices, Inc.
+## Copyright (c) 2018 - 2026 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
 
 PROJECT_NAME := admx100x_evb_zed
 
+M_DEPS += ../common/admx100x_evb_bd.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc
 M_DEPS += ../../common/zed/zed_system_bd.tcl
 M_DEPS += ../../../library/xilinx/common/ad_data_clk.v
+M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
 LIB_DEPS += axi_clkgen
@@ -18,6 +20,10 @@ LIB_DEPS += axi_hdmi_tx
 LIB_DEPS += axi_i2s_adi
 LIB_DEPS += axi_spdif_tx
 LIB_DEPS += axi_sysid
+LIB_DEPS += spi_engine/axi_spi_engine
+LIB_DEPS += spi_engine/spi_engine_execution
+LIB_DEPS += spi_engine/spi_engine_interconnect
+LIB_DEPS += spi_engine/spi_engine_offload
 LIB_DEPS += sysid_rom
 LIB_DEPS += util_i2c_mixer
 

projects/admx100x_evb/zed/system_bd.tcl

@@ -12,3 +12,5 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_
 ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
 
 sysid_gen_sys_init_file
+
+source ../common/admx100x_evb_bd.tcl

projects/admx100x_evb/zed/system_constr.xdc

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -23,8 +23,20 @@ set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33}                 [get_po
 set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33}                 [get_ports admx100x_ot];       ##H16   FMC_LA11_P
 
 # syncronization
+
 set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33}                 [get_ports admx100x_sync_mode]; ##H22  FMC_LA19_P  SYNC_MODE
 
+# RX part
+
+set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33}                 [get_ports acq_synq_in_fmc];  ## C10   FMC-LA06_P
+set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33}                 [get_ports acq_sclk];         ## D8    FMC-LA01 CC P
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33}                 [get_ports acq_drdy];         ## D12   FMC-LA05 N
+set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33}                 [get_ports acq_mclk];         ## G6    FMC-LA00 CC P
+set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33}                 [get_ports acq_mosi];          ## G9    FMC-LA03_P
+set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33}                 [get_ports acq_reset];        ## G15   FMC-LA12_P
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33}                 [get_ports acq_miso];         ## H7    FMC-LA02_P
+set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33}                 [get_ports acq_cs];           ## H11   FMC-LA04_N
+
 # set IOSTANDARD according to VADJ 3.3V
 
 set_property  -dict {IOSTANDARD LVCMOS33} [get_ports otg_vbusoc]