Add optimized YOLOv10n ONNX reference port (721s to ~8s on ET-SoC1) - #224

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ruimouradev wants to merge 11 commits into

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ruimouradev:port/yolov10n-onnx-reference

Commits on Jul 26, 2026

feat(yolo): add pinned ONNX YOLOv10n reference port
ruimouradev
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c388f3a
refactor(yolo): simplify reference port tooling
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cd393d6
draft 1: split Conv across 16 harts, rest single-hart, board time 721s to 69s
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5d6a97c
draft 2: -O2 build with 4KiB stack, 2-channel conv blocking, exponential barrier backoff, board time 69s to 34s
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61bfc3c
draft 3: elementwise multi-hart and dedicated 1x1 conv path
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0360c3d
Fuse SiLU and run its sigmoid on the vector unit
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b017c33
Run the 1x1 conv on the vector unit
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2746676
Split MatMul across harts by output rows
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6345312
Parallelize the decode and sppf serial ops across harts and short-circuit topk
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ff427a3
Parallelize Split, Reshape and ReduceMax across harts and vectorize the depthwise 3x3 conv
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bdd886b
Register the YOLOv10n reference port with the board benchmark harness
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58d1adb