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[sw-sysemu] fix wrong SRAM_BASE in pma_bootrom_cacheop test #118

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Merged
glguida merged 1 commit into from
Apr 1, 2026
Merged

[sw-sysemu] fix wrong SRAM_BASE in pma_bootrom_cacheop test #118

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2 changes: 1 addition & 1 deletion sw-sysemu/memory/erbium/main_memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ namespace bemu {
// | 0x00_0200_0000 | 0x00_0200_0FFF | 4KiB | SystemRegisters |
// | 0x00_0200_4000 | 0x00_0200_4FFF | 4KiB | UART |
// | 0x00_0200_A000 | 0x00_0200_BFFF | 8KiB | Boot ROM |
// | 0x00_0200_E000 | 0x00_0200_EFFF | 4KiB | Scratch SRAM |
// | 0x00_0200_C000 | 0x00_0200_CFFF | 4KiB | Scratch SRAM |
// | 0x00_4000_0000 | 0x00_40FF_FFFF | 16MiB | MRAM |
// | 0x00_7FFF_D000 | 0x00_7FFF_FFFF | 12KiB | OTP (read-only) |
// | 0x00_8000_0000 | 0x00_80FF_FFFF | 16MiB | ESR Registers |
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2 changes: 1 addition & 1 deletion sw-sysemu/tests/erbium/src/pma_bootrom_cacheop.c
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Expand Up @@ -14,7 +14,7 @@
#include "test.h"

#define MRAM_BASE 0x40000000ull
#define SRAM_BASE 0x0200E000ull
#define SRAM_BASE 0x0200C000ull
#define BOOTROM_BASE 0x0200A000ull

/* CSR addresses */
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