fix(nixl): fall back to per-tensor registration on a multi-allocation arena - #634
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… arena A CUDA fabric/IPC handle names exactly one cuMemCreate allocation. UCX cuda_ipc resolves a registered region with cuMemRetainAllocationHandle and cuMemGetAddressRange, which report the first allocation under the range rather than the whole reserve, so registering a multi-allocation arena as a single MR publishes an rkey covering only its first chunk. The peer then reads past what it mapped: measured on GB200 MNNVL as a segfault in cuMemcpyDtoDAsync_v2 with Kimi-K3 (arena over 1019 chunks, 3118 tensors, 139.74 GB). Fall back to per-tensor registration when the arena spans more than one physical allocation. Per-tensor is correct because the arena does one cuMemCreate per allocation, so each tensor lies wholly inside one handle, and it is already the default registration mode. The single-MR path stays valid on dmabuf/IB, where ibv_reg_dmabuf_mr does span multiple handles, so MX_ARENA_SINGLE_MR=1 keeps it. Measured on Kimi-K3, TP16 x 2 groups: 139.74 GB in 0.66-0.77 s (1446-1682 Gbps), model load 5.4 s versus 238 s from disk. Registration cost of the fallback: 0.001 s -> 1.1 s, metadata 801 B -> 805 KB. Signed-off-by: Zhongdongming Dai <zhongdongmin@nvidia.com>
Adds unit coverage for the new predicate: a multi-allocation arena registers per tensor, a single-allocation arena keeps the one MR, MX_ARENA_SINGLE_MR=1 keeps it either way, the fallback bypasses pool-reg, and the warning names the allocation count. The existing FakeArena fixtures gain live_allocation_count, which the real VmmArena already exposes. Documents MX_ARENA_SINGLE_MR and adds a 'Multi-handle arenas' section covering why a single MR cannot be addressed by cuda_ipc, why UCX_CUDA_COPY_REG_WHOLE_ALLOC=off does not cover that case, and the upstream UCX fixes in flight for both sides. Signed-off-by: Zhongdongming Dai <zhongdongmin@nvidia.com>
WalkthroughChangesArena registration behavior
Estimated code review effort: 3 (Moderate) | ~20 minutes Mergeability Score: 🟠 High · up to The arena registration path currently raises a TypeError before registration, so the multi-allocation fallback cannot operate for affected deployments; this high-impact correctness issue should be fixed before merge. A separate documentation lint issue also remains. Poem
🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches 💡 1🛠️ Fix failing CI checks 💡
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Inline comments:
In `@docs/DEPLOYMENT.md`:
- Line 704: Update the fenced log example in the deployment documentation to
specify the text language identifier, changing the opening fence to use text
while preserving the example content.
In `@modelexpress_client/python/modelexpress/nixl_transfer.py`:
- Around line 458-459: Call VmmArena.live_allocation_count in the live_allocs
check within modelexpress_client/python/modelexpress/nixl_transfer.py lines
458-459. Update each FakeArena definition at
modelexpress_client/python/tests/test_pool_registration.py lines 226-229,
243-246, 262-265, and 570-574 to provide live_allocation_count(self) methods
instead of integer attributes, preserving their existing returned counts.
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docs/ARCHITECTURE.mddocs/DEPLOYMENT.mdmodelexpress_client/python/modelexpress/envs.pymodelexpress_client/python/modelexpress/nixl_transfer.pymodelexpress_client/python/tests/test_pool_registration.py
Signed-off-by: Zhongdongming Dai <zhongdongmin@nvidia.com>
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/ok to test fc111af |
The arena's docs presented UCX_CUDA_COPY_REG_WHOLE_ALLOC=off as the complete deployment precondition and described multi-handle single-MR registration as validated without naming a transport. Both are true only on dmabuf/IB. On cuda_ipc a fabric handle names one cuMemCreate allocation, so a single MR over a multi-allocation arena publishes an rkey covering only the first chunk. - scope the cuda_copy knob in both env tables and in vmm/README.md - add a Transport support section and a cuda_ipc known limitation - fix the register_arena docstring, which asserted validation directly above the fallback that same function performs - point at openucx/ucx#11283 for the upstream cuda_ipc fix Signed-off-by: Nicolas 'Pixel' Noble <nicolas@nobis-crew.org>
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hope you don't mind, i pushed a docs commit onto your branch (116cae0) instead of a separate PR since it's the same subject. the arena docs presented UCX_CUDA_COPY_REG_WHOLE_ALLOC=off as the whole deployment precondition and called multi-handle single-MR registration validated without naming a transport. vmm/README.md had it as "required deployment flag" and listed no transport limitation at all. your new DEPLOYMENT.md section covers it in one place, this carries the same scoping to the other five, including register_arena's docstring, which claimed validation right above the fallback it now performs. might be worth linking openucx/ucx#11283 from the PR body, it's the upstream cuda_ipc fix for this, which makes the fallback a workaround with an exit. also #11461 merged, so the cuda_copy knob is only needed on builds predating it and i've reworded those. revert anything you don't like, it's your branch. |
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/ok to test 116cae0 |
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@nicolasnoble thanks for adding these. The unified scoping across the other doc location makes a lot of sense. Updated the PR description with link to 11283 as suggested |
3 participants
Problem
On GB200/GB300 MNNVL, a ModelExpress P2P receive segfaults when the source
registered its weights through the VMM arena:
Root cause
A CUDA fabric/IPC handle names exactly one
cuMemCreateallocation. UCX'scuda_ipc resolves a registered region with
cuMemRetainAllocationHandle+cuMemGetAddressRange, and both report the allocation containing the pointer,not the whole VA reserve.
register_arenaregisters[base, base+used)as oneMR, so the published rkey covers only the arena's first chunk; the peer maps
that much and then reads past it.
Measured on Kimi-K3, TP16: the arena reports
live_allocs=1019under a singleRegistered arena as 1 region from 3118 tensors.Two things this is not:
outside
[base, base+used)"; with the arena on, all 3118 are inside.UCX_CUDA_COPY_REG_WHOLE_ALLOC=off, whichregister_arena's docstringrecommends, does not help — the truncation is in cuda_ipc, not cuda_copy,
and UCX 1.21 has no cuda_ipc equivalent:
UCX WARN unused environment variable: UCX_CUDA_IPC_REG_WHOLE_ALLOC (maybe: UCX_CUDA_COPY_REG_WHOLE_ALLOC?)Fix
Fall back to per-tensor registration when the arena spans more than one physical
allocation. Per-tensor is correct because the arena does one
cuMemCreateperallocation, so every tensor lies wholly inside one handle — and it is already
the default registration mode, so this is a well-trodden path rather than a new
one.
The single-MR path stays valid on dmabuf/IB, where
ibv_reg_dmabuf_mrgenuinelydoes span several handles (as the function's own docstring records), so
MX_ARENA_SINGLE_MR=1keeps it for those deployments.Deliberately not attempted: making one MR cover a multi-allocation arena.
That is not expressible at the CUDA API level; it would require the arena to
preallocate its whole budget in a single
cuMemCreate, giving up lazy growth.Measured
Kimi-K3 (2.8T, MXFP4), TP16 x 2 groups, 8x GB200 in one NVLink clique, MNNVL
cuda_ipc, ModelExpress client and server both built from this branch:
cuMemcpyDtoDAsync_v2Three consecutive runs, both groups restarted each time, no segfault. The lane
is confirmed to be the same one that used to fail:
Weight integrity: source loaded from disk, target loaded over P2P, 16
prompts at
temperature=0, seed=0— all 16 outputs byte-identical (SHA1 match),including four that ran to
max_tokens. Repeated withPYTORCH_ALLOC_CONF=expandable_segments:Trueremoved: identical again, andbyte-identical to the run with it set (with the arena on, weights bypass torch's
allocator, so that flag is irrelevant to this path).
The fallback costs ~1.1 s of registration and 805 KB of metadata against 233 s
of disk load saved.
Test plan
byte-identical inference output
Related upstream bug fix: openucx/ucx#11283
Summary by CodeRabbit
New Features
MX_ARENA_SINGLE_MR=1.Documentation