verilog backend: preserve signed on wire and port declarations

[alaindargelas]

dump_wire had no code path that emits the signed keyword for wires/ports whose RTLIL is_signed flag is set. Reading

module top(input signed [9:0] in, output signed [31:0] o);
assign o = in;
endmodule

and writing it back via write_verilog produced

input [9:0] in;
output [31:0] o;

losing the declared signedness even though wire->is_signed was tracked correctly in RTLIL throughout the round trip. The IEEE 1364-2001 grammar (Annex A.2.1.2 / A.2.1.3) allows signed after the direction / net-type keyword, which is the dialect write_verilog targets by default — so the fix is to emit signed between the direction/net-type and the range when wire->is_signed.

Closes the half of chipsalliance/synlig#2425 that lives in Yosys: the SystemVerilog frontend correctly produces a signed wire for output int, but the Verilog backend dropped it on write.

Adds tests/various/write_verilog_signed_port.ys, which round-trips a module with signed inputs, outputs, and an internal wire and greps for the keyword on each declaration — fails without the fix, passes with it.

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[widlarizer]

@Goubermouche does #5771 cover this too?

[Goubermouche]

@widlarizer Seems like it, the provided test cases passes under #5771 too.